Asynchronous fifo buffer with johnson code write pointer

A system for transferring input data to an asynchronous clock domain, the system comprising:

• a bus interface unit connected to a data bus for receiving the input data, and generating a write increment signal based on a length of the input data;
• a first-in-first-out (FIFO) write logic module, connected to the bus interface unit, for receiving a write clock signal and the write increment signal, incrementing a write address count value, encoding the write address count value using a Johnson code, and generating a write pointer and a write address signal;
• a write pointer synchronizer, connected to the FIFO write logic module, for receiving a read clock signal and the write pointer and outputting a synchronized write pointer;
• a write pointer validator, connected to the write pointer synchronizer, for receiving the synchronized write pointer, and generating a write pointer valid signal when the synchronized write pointer conforms to a Johnson code format;
• a FIFO read logic module for receiving the read clock signal and a read increment signal, and connected to the write pointer synchronizer and the write pointer validator for receiving the synchronized write pointer and the write pointer valid signal, respectively, decoding the synchronized write pointer, generating a synchronized write address count value, incrementing a read address count value based on the read increment signal and the synchronized write address count value, and generating a read address signal;
• and
• an asynchronous first-in-first-out (FIFO) buffer connected to the FIFO write and FIFO read logic modules for receiving the write address and the read address signals, respectively, and to the bus interface unit for receiving the input data, for storing the input data based on the write address signal, and transferring the input data to the asynchronous clock domain based on the read address signal.

A method for transferring input data from a first clock domain to a second clock domain, the method comprising:

• incrementing a write address count value based on a write increment signal;
• generating a write address signal based on a write address count value;
• receiving the input data from the first clock domain and storing the input data in an asynchronous first-in-first-out (FIFO) buffer based on the write address signal;
• encoding the write address count value using a Johnson code and generating a write pointer at the first clock domain;
• generating a synchronized write pointer based on the write pointer;
• receiving the synchronized write pointer at the second clock domain;
• generating a write pointer valid signal when the synchronized write pointer conforms to a Johnson code format;
• decoding the synchronized write pointer based on the write pointer valid signal and generating a synchronized write address count value;
• incrementing a read address count value based on a read increment signal and the synchronized write address count value;
• generating a read address signal;
• and
• transferring the input data from the asynchronous FIFO buffer to the second clock domain based on the read address signal.