Method and apparatus for bit-to-bit timing correction of a high speed memory bus

A method of capturing sets of digital signals applied to a digital device, the digital signals in each set being applied to respective latches in the digital device and the respective digital signals having data eyes that are offset relative to each other, comprising:

• placing the digital device in a synchronization mode of operation;
• generating a plurality of internal clock signals responsive to an external clock signal, each internal clock signal being applied to an associated latch and having a phase shift relative to the external clock signal;
• adjusting the respective phase shifts of the internal clock signals;
• storing each of the digital signals in each of the sets in the corresponding latch responsive to the associated internal clock signal at the adjusted phases;
• determining a final phase shift for each internal clock signal that causes the internal clock signal to clock the corresponding latch during the data eye of the corresponding digital signal;
• and
• clocking each of the latches with the corresponding internal clock signal having the determined final phase shift.

A method of capturing a set of digital signals applied to a digital device, comprising:

• placing the digital device in a synchronization mode of operation;
• repetitively applying sets of the digital signals having expected values to the digital device;
• generating a plurality of internal clock signals responsive to an external clock signal, each internal clock signal having a phase relative to an associated digital signal in the set of digital signals;
• storing in the digital device each of the digital signals in a plurality of sets responsive to different phases of the associated internal clock signals;
• evaluating the stored digital signals to determine if the stored digital signals have the expected values;
• identifying the phases of each internal clock signal that caused the associated digital signal having the expected values to be stored;
• selecting a phase for each of the internal clock signals from among the phases that caused the digital signal having the expected values to be stored;
• adjusting the phase of each of the internal clock signals to the corresponding selected phase;
• and
• storing each of the digital signals in applied sets responsive to the associated internal clock signal having the selected phase.

A synchronization circuit for capturing sets of digital signals applied to a digital device, the digital signals in each set being applied to respective latches in the digital device, comprising:

• a clock generator circuit generating a plurality of internal clock signals on respective outputs responsive to an external clock signal, each internal clock signal having a corresponding phase relative to the external clock signal;
• a plurality of selection circuits, each selection circuit having inputs coupled to respective outputs of the clock generator circuit and having an output coupled to a clock terminal of an associated latch, the selection circuit coupling a selected input to its output responsive to a phase command signal;
• an evaluation circuit coupled to receive a plurality of digital signals sequentially stored in a selected one of the latches, and generating a results signal indicating whether each of the digital signals has an expected value;
• and
• a control circuit coupled to the evaluation circuit and the selection circuits, the control circuit sequentially selecting the latches and operable for each selected latch to adjust the phase command signals applied to the selection circuit coupled to the selected latch, store results signals received from the evaluation circuit at respective phase command signals, and generate a final phase command signal from the stored results signals, the control circuit applying each final phase command signal to the corresponding selection circuit to capture respective digital signals in subsequently applied packet words responsive to the internal clock signals having respective phases corresponding to the respective final phase command signals.

A dynamic random access memory, comprising:

• a clock generator circuit generating a plurality of internal clock signals on respective outputs responsive to an external clock signal, each internal clock signal having a corresponding phase relative to the external clock signal;
• at least one array of memory cells adapted to store data at a location determined by a row address and a column address, each of the addresses corresponding to a set of digital signals;
• a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to a first set of command signals;
• a column address circuit adapted to receive or apply data to one of the memory cells in the selected row corresponding to the column address responsive to a second set of command signals;
• a data path circuit adapted to couple a set of digital signals corresponding to data between an external data bus and the column address circuit responsive to a third set of command signals;
• a command buffer receiving a memory command corresponding to a set of digital signals and generating the first, second and third sets of command signals responsive thereto;
• a plurality of latches that store respective digital signals in one of the sets of digital signals responsive to transitions of respective internal clock signals;
• and
• a synchronization circuit for capturing the digital signals in at least one of the sets of digital signals, the synchronization circuit comprising,
• a plurality of selection circuits, each selection circuit having inputs coupled to respective outputs of the clock generator circuit and having an output coupled to a clock terminal of an associated one of the latches, the selection circuit coupling a selected input to its output responsive to a phase command signal;
• an evaluation circuit coupled to receive a plurality of digital signals sequentially stored in a selected one of the latches, and generating a results signal indicating whether each of the digital signals has an expected value;
• and
• a control circuit coupled to the evaluation circuit and the selection circuits and adapted to receive a synchronization signal, the control circuit operable when the synchronization signal goes active to sequentially select the latches and operable for each selected latch to adjust the phase command signals applied to the selection circuit coupled to the selected latch, store results signals sequentially received from the evaluation circuit at respective phase command signals, and generate a final phase command signal from the stored results signals, the control circuit applying each final phase command signal to the corresponding selection circuit to capture respective digital signals in subsequently applied sets of the digital signals responsive to the internal clock signals having respective phases corresponding to the respective final phase command signals.

A computer system, comprising:

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
• and
• a dynamic random access memory coupled to the processor bus, comprising,
• a clock generator circuit generating a plurality of internal clock signals on respective outputs responsive to an external clock signal, each internal clock signal having a corresponding phase relative to the external clock signal;
• at least one array of memory cells adapted to store data at a location determined by a row address and a column address, each of the addresses corresponding to a set of digital signals;
• a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to a first set of command signals;
• a column address circuit adapted to receive or apply data to one of the memory cells in the selected row corresponding to the column address responsive to a second set of command signals;
• a data path circuit adapted to couple a set of digital signals corresponding to data between an external data bus and the column address circuit responsive to a third set of command signals;
• a command buffer receiving a memory command corresponding to a set of digital signals and generating the first, second and third sets of command signals responsive thereto;
• a plurality of latches that store respective digital signals in one of the sets of digital signals responsive to transitions of respective internal clock signals;
• and
• a synchronization circuit for capturing the digital signals in at least one of the sets of digital signals, the synchronization circuit comprising,
• a plurality of selection circuits, each selection circuit having inputs coupled to respective outputs of the clock generator circuit and having an output coupled to a clock terminal of an associated one of the latches, the selection circuit coupling a selected input to its output responsive to a phase command signal;
• an evaluation circuit coupled to receive a plurality of digital signals sequentially stored in a selected one of the latches, and generating a results signal indicating whether each of the digital signals has an expected value;
• and
• a control circuit coupled to the evaluation circuit and the selection circuits and adapted to receive a synchronization signal, the control circuit operable when the synchronization signal goes active to sequentially select the latches and operable for each selected latch to adjust the phase command signals applied to the selection circuit coupled to the selected latch, store results signals sequentially received from the evaluation circuit at respective phase command signals, and generate a final phase command signal from the stored results signals, the control circuit applying each final phase command signal to the corresponding selection circuit to capture respective digital signals in subsequently applied sets of the digital signals responsive to the internal clock signals having respective phases corresponding to the respective final phase command signals.

A synchronization circuit for capturing sets of digital signals applied to a memory device, the digital signals in each set being applied to respective latches in the memory device, comprising:

• a clock generator including an input and a plurality of outputs, the clock generator developing a plurality of internal clock signals on respective outputs responsive to the external clock signal, each internal clock signal having a corresponding phase relative to the external clock signal;
• a plurality of selection circuits, each selection circuit having inputs coupled to respective outputs of the clock generator circuit and having an output coupled to a clock terminal of an associated latch, the selection circuit coupling a selected input to its output responsive to a phase command signal;
• an evaluation circuit having inputs coupled to receive a plurality of digital signals stored in a selected one of the latches, and having an output, the evaluation circuit coupling its output to a first voltage responsive to each of the digital signals having an expected value, and coupling its output to a second voltage responsive to any of the digital signals not having the expected value;
• and
• a control circuit coupled to the evaluation circuit and the selection circuits, the control circuit applying the digital signals stored in a selected one of the latches to the evaluation circuit, sequentially adjusting the phase command signal applied to the selection circuit coupled to the selected latch, and storing values output from the evaluation circuit responsive to the applied digital signals for each phase command signal, and thereafter generating a final phase command signal from the stored values output from the evaluation circuit, and the control circuit thereafter sequentially selecting each latch and determining a final phase command signal that is applied to the selection circuit coupled to the selected latch.