FIFO memory system and method with improved determination of full and empty conditions and amount of data stored

A method of operating a first in, first out (FIFO) memory system including a memory having a plurality of locations each having an address, the method comprising the steps of:

• at a selected moment in time, generating a current write address associated with a location within the memory to which a write operation is to be performed, and a current read address associated with a location within the memory from which a read operation is to be performed, wherein the current write address and the current read address are generated in accordance with a circular counting sequence;
• generating an EMPTY control signal when the current write address is equal to the current read address at the selected moment in time;
• and
• generating a FULL control signal when the current write address is equal to a last-used read address at the selected moment in time, wherein the last-used read address immediately precedes the current read address in the circular counting sequence,
• wherein generating the EMPTY control signal comprises:
• converting the current read address into a series of sequential Gray-code read address values including a next-to-be-used Gray-code read address value, a current Gray-code read address value, and a last-used Gray-code read address value;
• converting the current write address into a series of sequential Gray-code write address values including a next-to-be-used Gray-code write address value and a current Gray-code write address value;
• comparing the next-to-be-used Gray-code read address value and the current Gray-code write address value, and generating an ALMOST_EMPTY control signal when the next-to-be-used Gray-code read address value is equal to the current Gray-code write address value during a read operation;
• and
• generating the EMPTY control signal within one clock cycle following the generation of the ALMOST_EMPTY control signal.

A method of operating a first in, first out (FIFO) memory system including a memory having a plurality of locations each having an address, the method comprising the steps of:

• at a selected moment in time, generating a current write address associated with a location within the memory to which a write operation is to be performed, and a current read address associated with a location within the memory from which a read operation is to be performed, wherein the current write address and the current read address are generated in accordance with a circular counting sequence;
• generating an EMPTY control signal when the current write address is equal to the current read address at the selected moment in time;
• and
• generating a FULL control signal when the current write address is equal to a last-used read address at the selected moment in time, wherein the last-used read address immediately precedes the current read address in the circular counting sequence,
• wherein generating the FULL control signal comprises:
• converting the current read address into a series of sequential Gray-code read address values including a next-to-be-used Gray-code read address value, a current Gray-code read address value, and a last-used Gray-code read address value;
• converting the current write address into a series of sequential Gray-code write address values including a next-to-be-used Gray-code write address value and a current Gray-code write address value;
• comparing the next-to-be-used Gray-code write address value and the last-used Gray-code read address value, and generating an ALMOST_FULL control signal when the next-to-be-used Gray-code write address value is equal to the last-used Gray-code read address value during a write operation;
• and
• generating the FULL control signal within one clock cycle following the generation of the ALMOST_FULL control signal.

A method of operating a first in, first out (FIFO) memory system including a memory having a plurality of locations each having an address, the method comprising the steps of:

• at a selected moment in time, generating a current write address associated with a location within the memory to which a write operation is to be performed, and a current read address associated with a location within the memory from which a read operation is to be performed, wherein the current write address and the current read address are generated in accordance with a circular counting sequence;
• generating an EMPTY control signal when the current write address is equal to the current read address at the selected moment in time;
• and
• generating a FULL control signal when the current write address is equal to a last-used read address at the selected moment in time, wherein the last-used read address immediately precedes the current read address in the circular counting sequence,
• wherein generating the EMPTY control signal comprises:
• converting the current read address into a series of sequential Gray-code read address values including a next-to-be-used Gray-code read address value, a current Gray-code read address value, and a last-used Gray-code read address value;
• converting the current write address into a series of sequential Gray-code write address values including a next-to-be-used Gray-code write address value and a current Gray-code write address value;
• generating first and second logic signals, the first logic signal having a logic value determined by comparing the next-to-be-used Gray-code read address value and the current Gray-code write address value, and the second logic signal having a logic value determined by comparing the current Gray-code read address value and the current Gray-code write address value;
• and
• selectively passing one of the first logic signal and the second logic signal to control a carry chain, wherein the first logic signal is passed to control the carry chain when the EMPTY control signal has a first logic level, and the second logic signal is passed to control the carry chain when the EMPTY control signal has a second logic level.

A method of operating a first in, first out (FIFO) memory system including a memory having a plurality of locations each having an address, the method comprising the steps of:

• at a selected moment in time, generating a current write address associated with a location within the memory to which a write operation is to be performed, and a current read address associated with a location within the memory from which a read operation is to be performed, wherein the current write address and the current read address are generated in accordance with a circular counting sequence;
• generating an EMPTY control signal when the current write address is equal to the current read address at the selected moment in time;
• and
• generating a FULL control signal when the current write address is equal to a last-used read address at the selected moment in time, wherein the last-used read address immediately precedes the current read address in the circular counting sequence,
• wherein generating the FULL control signal comprises:
• converting the current read address into a series of sequential Gray-code read address values including a next-to-be-used Gray-code read address value, a current Gray-code read address value, and a last-used Gray-code read address value;
• converting the current write address into a series of sequential Gray-code write address values including a next-to-be-used Gray-code write address value and a current Gray-code write address value;
• generating first and second logic signals, the first logic signal having a logic value determined by comparing the last used Gray-code read address value and the next-to-be-used Gray-code write address value, and the second logic signal having a logic value determined by comparing the last-used Gray-code read address value and the current Gray-code write address value;
• and
• selectively passing one of the first logic signal and the second logic signal to control a carry chain, wherein the first logic signal is passed to control the carry chain when the FULL control signal has a first logic level, and the second logic signal is passed to control the carry chain when the FULL control signal has a second logic level.