Gray code counter enabled to increment by greater than one
AssigneeSynopsys, Inc.
InventorAlan Geist
Life of this patent
Estimating the term…
Abstract
A Gray code counter is enabled to increment by greater than one and still obey a rule of only one bit of change. The Gray code counter has applicability, for example, with use with an arbiter to control a multi-input asynchronous FIFO usable to synchronize data transfers between asynchronous source and destination clock domains.
Claims20
A circuit for providing multiple inputs to a single output, the circuit comprising:
- a first in first out (FIFO) synchronizing circuit for synchronizing the multiple inputs driven by a source clock to a single output driven by a destination clock;
- and
- an arbiter including a Gray code counter for controlling the FIFO synchronizing circuit to arbitrate provision of the multiple inputs to the single output, wherein the Gray code counter is enabled to:
- increment or decrement a Gray code count by one, and
- increment the Gray code count by an additional number greater than one for some increments of the Gray code count,
- wherein the Gray code count is used to generate write pointer signals that include a first write pointer value and a second write pointer value,
- wherein the first write pointer value is used for selecting one or more outputs of multiple outputs of a source multiplexer, and
- wherein the second write pointer value is used for selecting one or more storage elements to store one or more of the selected outputs of the source multiplexer.
A method of operating a circuit for providing multiple inputs to a single output, the method comprising:
- synchronizing the multiple inputs driving by a source clock to a single output driven by a destination clock;
- implementing an arbiter including a Gray code counter to control the synchronizing to arbitrate provision of the multiple inputs to the single output;
- and
- implementing the Gray code counter to:
- increment or decrement a Gray code count by one, and
- increment the Gray code count by an additional number greater than one for some increments of the Gray code count, and
- wherein the Gray code count is used to generate write pointer signals that include a first write pointer value and a second write pointer value, and
- wherein the method includes:
- implementing the first write pointer value to select one or more outputs of multiple outputs of a source multiplexer, and
- implementing the second write pointer value to select one or more storage elements to store one or more of the selected outputs of the source multiplexer.
A non-transitory computer readable medium comprising stored instructions for providing multiple inputs to a single output, the stored instructions, when executed by a processor, causing the processor to:
- synchronize the multiple inputs driving by a source clock to a single output driven by a destination clock;
- implement an arbiter including a Gray code counter to control the synchronizing to arbitrate provision of the multiple inputs to the single output;
- and
- implement the Gray code counter to:
- increment or decrement a Gray code count by one, and
- increment the Gray code count by an additional number greater than one for some increments of the Gray code count,
- wherein the Gray code count is used to generate a shared write pointer, and
- wherein the instructions, when executed by the processor, cause the processor to implement the shared write pointer to both select one or more outputs of multiple outputs of a source multiplexer and to select one or more storage elements to store one or more of the selected outputs of the source multiplexer.
Dependencies are inferred from the claim text.