Systems and methods for gray coding based error correction in an asynchronous counter
AssigneeMarvell International Ltd.
InventorsLuns Tee, Wanghua Wu, Xiang Gao
Life of this patent
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Abstract
Embodiments described herein provide a method for correcting a propagation delay induced error in an output of an asynchronous counter. An input clock is applied to the asynchronous counter. A gray-code count is generated by the asynchronous counter. The gray-code count is mapped to a binary count. An error component, indicative of a counting error induced by a propagation delay between the input clock and the binary count, is generated by taking an exclusive-OR operation over the gray-code count and the input clock. The error component is added to the binary count to generate an error-corrected binary count. The error-corrected binary count is output.
Claims20
A method for correcting a propagation delay induced error in an output of an asynchronous counter, the method comprising:
- applying an input clock to a gray-code counter;
- generating a gray-code count by the gray-code counter;
- mapping the gray-code count to a binary count;
- generating an error component, indicative of a counting error induced by a propagation delay between the input clock and the binary count, by taking an exclusive-OR operation over the gray-code count and the input clock;
- adding the error component to the binary count to generate an error-corrected binary count;
- and
- outputting the error-corrected binary count.
A system for correcting a propagation delay induced error in an output of an asynchronous counter, the system comprising:
- a first gray-to-binary count converter configured to:
- receive a gray-code count generated by the gray-code counter, wherein the gray-code counter is operated by an input clock,
- map the gray-code count to a binary count;
- an exclusive OR gate configured to perform an exclusive-OR operation over the gray-code count and the input clock to generate an error component indicative of a counting error induced by a propagation delay between the input clock and the binary count;
- and
- an adder to generate an error-corrected binary count by adding the error component to the binary count.
Dependencies are inferred from the claim text.