Loading patent…
AssigneeSharp Kabushiki Kaisha
InventorsMichael A. Csoppenszky, Yoshikazu Nishiura
Estimating the term…
Method and apparatus are described for generating more accurate and timely FIFO status flags. Preferably, the asynchronous FIFO read and write pointers are conventionally compared with one another and the output of such comparison is glitch-suppressed. During such operation in accordance with the invented method and apparatus, prediction signals are used to precondition the status flag output latches so that they will provide the earliest possible accurate status reflecting asynchronous read and write clock activity. If a boundary condition is present--e.g. depending upon the next read or write clock activity, the FIFO's half full status flag may change where such change is impossible to predict because it is unknowable whether the next operation will be a read or a write or both--then an asynchronous state machine takes over from the prediction flag logic to ensure accurate and early preconditioning of the status flags' output latches. When no such boundary condition is present, the state machine is dormant and the prediction logic is active.
In a first-in first-out memory device (FIFO) which includes read and write address pointers, wherein the read address pointer is indexed synchronously with a read clock signal and the write address pointer is indexed synchronously with a write clock signal, such read and write clock signals being asynchronously pulsed relative to one another, a status flag generation apparatus comprising:
For use in connection with a first-in first-out memory device (FIFO) having read and write address pointers capable of asynchronous indexing, a status flag generation method which comprises:
For use in the generation of a status flag in a first-in first-out memory device which includes a read address pointer indexed by a read clock and a write address pointer indexed by a write clock, a method which comprises:
Dependencies are inferred from the claim text.