G06F 2117/12
Sizing
Official title: Sizing, e.g. of transistors or gates
G06F2117/12 (Sizing) appears on 61 US grants and 101 published applications in this corpus.
Search patents in G06F- Granted patents
- 61
- Published applications
- 101
- Assignees
- 43
- Inventors
- 241
- Latest grant
- 22 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2005 | 0 | 1 |
| 2006 | 0 | 0 |
| 2007 | 0 | 0 |
| 2008 | 2 | 2 |
| 2009 | 1 | 1 |
| 2010 | 1 | 0 |
| 2011 | 0 | 2 |
| 2012 | 0 | 0 |
| 2013 | 1 | 0 |
| 2014 | 1 | 2 |
| 2015 | 1 | 1 |
| 2016 | 1 | 2 |
| 2017 | 2 | 3 |
| 2018 | 2 | 2 |
| 2019 | 2 | 2 |
| 2020 | 4 | 2 |
| 2021 | 2 | 8 |
| 2022 | 5 | 8 |
| 2023 | 9 | 16 |
| 2024 | 10 | 16 |
| 2025 | 11 | 15 |
| 2026 | 6 | 18 |
By publication year. 2026 runs to 8 Oct.
Recent patents
- Systems and methods for designing a discrete device product22 Sep 2026US 12,743,567 B2Semiconductor Components Industries, LLC
- Integrated circuit design method, system and computer program product28 Apr 2026US 12,614,016 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Integrated circuit including standard cell and method of manufacturing the integrated circuit21 Apr 2026US 12,608,530 B2Samsung Electronics Co., Ltd.
- Wafer-scale chip structure and method and system for designing the structure10 Mar 2026US 12,575,426 B2GLOBALFOUNDRIES U. S. Inc.
- Method of RF analog circuits electronic design automation based on gcn and deep reinforcement learning10 Feb 2026US 12,547,805 B2Mitsubishi Electric Research Laboratories, Inc.
- Method for alleviating leakage degradation effect in gan device3 Sep 2026US 2026/0262262 A1Beijing Satellite Factory Co., Ltd.
- Method and apparatus with two-dimensional cell placement optimization13 Aug 2026US 2026/0236663 A1Samsung Electronics Co., Ltd.
- Integrated circuit design method, system and computer program product30 Jul 2026US 2026/0220349 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Method for system for automatically generating the design rule document of a semiconductor device9 Jul 2026US 2026/0195518 A1AIP Technology Corporation
- Front-end-of-line floorplan of integrated circuit that has dummies inserted by blockage-aided dummy insertion and related method7 May 2026US 2026/0127350 A1Mediatek Inc.
Most cited
By later US patents
- Fragmentation point and simulation site adjustment for resolution enhancement techniques15US 7,861,207 B2Mentor Graphics Corporation · 2010
- Method for designing a CMOS sensor using parameters8US 7,334,211 B1ESS Technology, Inc. · 2008
- Semiconductor device including regions for reducing density gradient effect and method of forming the same5US 11,270,057 B1Taiwan Semiconductor Manufacturing Company.Ltd · 2022
- Power aware resizing of clock tree instances4US 10,796,066 B1Cadence Design Systems, Inc. · 2020
- Fragmentation point and simulation site adjustment for resolution enhancement techniques4US 8,566,753 B2Mentor Graphics Corporation · 2013