Power aware resizing of clock tree instances

A method comprising:

• accessing an integrated circuit design stored in memory, the integrated circuit design comprising a clock tree comprising routes that interconnect a plurality of clock-tree instances;
• determining, by at least one hardware processor, a baseline power consumption measurement corresponding to a sub-tree of a first clock-tree instance from among the plurality of interconnected clock tree instances, the baseline power consumption measurement corresponding to a first size of the first clock tree instance, the determining of the baseline power consumption measurement comprising determining a sum of a first internal power consumption, a first switching power dissipation, and a first leakage power dissipation corresponding to the sub-tree of the first clock-tree instance with the first size of the first clock-tree instance;
• determining, by the at least one hardware processor, an alternative power consumption measurement corresponding to the sub-tree with the first clock-tree instance at a second size, the determining of the alternative power consumption measurement comprising determining a sum of a second internal power consumption, a second switching power dissipation, and a second leakage power dissipation corresponding to the sub-tree of the first clock-tree instance with the second size of the first clock tree instance;
• comparing the alternative power consumption measurement to the baseline power consumption measurement;
• based on determining the alternative power consumption measurement is less than the baseline power consumption measurement, upsizing, by the at least one hardware processor, the first clock-tree instance in the clock tree according to the second size;
• selecting a second clock-tree instance in the clock tree to evaluate for resizing based on a position of the second clock-tree instance in the clock tree relative to a position of the first clock tree instance in the clock tree:
• downsizing the second clock-tree instance in the clock tree in response to determining that downsizing the second clock-tree instance results in a reduction of power consumption in a sub-tree of the second clock-tree instance;
• and
• generating a layout instance for the integrated circuit design based on the upsized first clock-tree instance and the downsized second clock-tree instance, the layout instance describing physical layout dimensions of the integrated circuit design.

A computer storage medium storing instructions, which when executed by a machine, cause the machine to perform operations comprising:

• accessing an integrated circuit design stored in memory, the integrated circuit design comprising a clock tree comprising routes that interconnect a plurality of clock-tree instances;
• selecting, from among the plurality of clock-tree instances of the clock tree, a first clock-tree instance to evaluate for resizing, the first clock-tree instance initially being of a first size;
• determining a baseline power consumption measurement corresponding to a sub-tree of the first clock-tree instance, with the first clock-tree instance at the first size, the determining of the baseline power consumption measurement comprising determining a sum of a first internal power consumption, a first switching power dissipation, and a first leakage power dissipation corresponding to the sub-tree of the first clock-tree instance with the first size of the first clock-tree instance;
• determining a plurality of alternative power consumption measurements corresponding to the sub-tree of the first clock-tree instance, each alternative power consumption measurement corresponding to one of a plurality of alternative sizes of the first clock-tree instance, the determining of the plurality of alternative power consumption measurements comprising determining an alternative power consumption measurement corresponding to the sub-tree with the first clock-tree instance at a second size, the determining of the alternative power consumption measurement comprising determining a sum of a second internal power consumption, a second switching power dissipation, and a second leakage power dissipation corresponding to the sub-tree of the first clock-tree instance with the second size of the first clock tree instance;
• determining a lowest alternative power consumption measurement of the plurality of alternative power consumption measurements, the lowest alternative power consumption measurement corresponding to the second size of the first clock-tree instance;
• comparing the lowest alternative power consumption measurement with the baseline power consumption measurement;
• based on determining that the lowest alternative power consumption measurement is less than the baseline power consumption measurement, upsizing the first clock-tree instance in the clock tree from the first size to the second size;
• selecting the second clock-tree instance in the clock tree to evaluate for resizing based on a position of the second clock-tree instance in the clock tree relative to a position of the first clock tree instance in the clock tree:
• downsizing a second clock-tree instance in the clock tree in response to determining that downsizing the second clock-tree instance results in a reduction of power consumption in a sub-tree of the second clock-tree instance;
• and
• generating a layout instance for the integrated circuit design based on the upsized first clock-tree instance and the downsized second clock-tree instance, the layout instance describing physical layout dimensions of the integrated circuit design.