Integrated circuit design method, system and computer program product

A system for modifying a layout for an integrated circuit (IC), said system comprising:

• at least one processor;
• and
• a non-transitory computer readable storage medium connected to the processor, wherein the processor is configured to execute instructions stored on the computer readable storage medium to:
• select, in the layout, a circuit region to be scaled along a first direction,
• disconnect a first conductive pattern, which extends in a second direction transverse to the first direction and across a boundary of the selected circuit region, into an inner part in the selected circuit region and an outer part outside the selected circuit region,
• scale the selected circuit region along the first direction, and
• reconnect the inner part in the scaled circuit region and the outer part, in response to at least one of
• a first determination that the inner part in the scaled circuit region and the outer part are electrically disconnected from each other, or
• a second determination that at least one of the inner part in the scaled circuit region or the outer part fails a verification.

A computer program product, comprising a non-transitory, computer-readable medium containing instructions therein which, when executed by a processor, cause the processor to perform:

• selecting, in a layout for an integrated circuit (IC), a circuit region to be scaled along a first direction, wherein the selected circuit region comprises:
• devices having a plurality of gate patterns arranged at a first gate pattern pitch along the first direction,
• first conductive patterns extending along the first direction,
• second conductive patterns extending along a second direction transverse to the first direction, and
• vias;
• and
• scaling the selected circuit region along the first direction without changing a gate pattern width of the plurality of gate patterns to obtain a modified layout, wherein said scaling comprises
• performing re-placement of the devices with the plurality of gate patterns arranged at a second gate pattern pitch along the first direction, the second gate pattern pitch different from the first gate pattern pitch,
• rearranging one or more of the second conductive patterns and the vias along the first direction, based on a scaling factor being a ratio of the second gate pattern pitch to the first gate pattern pitch, and
• resizing one or more of the first conductive patterns along the first direction, based on the scaling factor.