G06F 13/4217
With synchronous protocol
Official title: {with synchronous protocol}
G06F13/4217 (With synchronous protocol) appears on 455 US grants and 192 published applications in this corpus.
Search patents in G06F- Granted patents
- 455
- Published applications
- 192
- Assignees
- 180
- Inventors
- 916
- Latest grant
- 18 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 2 | 0 |
| 1977 | 2 | 0 |
| 1978 | 1 | 0 |
| 1979 | 1 | 0 |
| 1980 | 3 | 0 |
| 1981 | 4 | 0 |
| 1982 | 2 | 0 |
| 1983 | 6 | 0 |
| 1984 | 5 | 0 |
| 1985 | 6 | 0 |
| 1986 | 6 | 0 |
| 1987 | 5 | 0 |
| 1988 | 8 | 0 |
| 1989 | 10 | 0 |
| 1990 | 12 | 0 |
| 1991 | 6 | 0 |
| 1992 | 8 | 0 |
| 1993 | 9 | 0 |
| 1994 | 13 | 0 |
| 1995 | 15 | 0 |
| 1996 | 18 | 0 |
| 1997 | 27 | 0 |
| 1998 | 23 | 0 |
| 1999 | 16 | 0 |
| 2000 | 15 | 0 |
| 2001 | 14 | 5 |
| 2002 | 19 | 16 |
| 2003 | 15 | 10 |
| 2004 | 14 | 13 |
| 2005 | 10 | 10 |
| 2006 | 14 | 12 |
| 2007 | 12 | 11 |
| 2008 | 14 | 15 |
| 2009 | 11 | 6 |
| 2010 | 12 | 8 |
| 2011 | 6 | 4 |
| 2012 | 7 | 5 |
| 2013 | 5 | 4 |
| 2014 | 7 | 8 |
| 2015 | 4 | 6 |
| 2016 | 7 | 7 |
| 2017 | 10 | 12 |
| 2018 | 13 | 7 |
| 2019 | 8 | 8 |
| 2020 | 6 | 5 |
| 2021 | 7 | 4 |
| 2022 | 2 | 3 |
| 2023 | 5 | 0 |
| 2024 | 5 | 5 |
| 2025 | 2 | 4 |
| 2026 | 3 | 4 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- System on chip18 Aug 2026US 12,711,091 B2Samsung Electronics Co., Ltd.
- Clock-to-data synchronization14 Jul 2026US 12,681,525 B2NVIDIA Corporation
- System-on-chip and an interconnect bus included in the system on chip21 Apr 2026US 12,608,327 B2Samsung Electronics Co., Ltd.
- Dynamic baseboard management controller memory use1 Jul 2025US 12,346,282 B2Lenovo Enterprise Solutions (Singapore) Pte.Ltd.
- Systems and methods for lane management in a communication bus11 Mar 2025US 12,248,422 B2QUALCOMM Incorporated
- Clock-to-data synchronization1 Oct 2026US 2026/0299641 A1NVIDIA Corporation
- Low-latency word alignment for serdes interfaces using inline patterns30 Jul 2026US 2026/0219701 A1QUALCOMM Incorporated
- Novel resource-optmized source synchronous data transfer2 Jul 2026US 2026/0187011 A1NXP USA, Inc.
- Virtualized PTM Master Time4 Jun 2026US 2026/0154227 A1Mellanox Technologies, Ltd.
- Clock-to-data synchronization18 Dec 2025US 2025/0383684 A1NVIDIA Corporation
Most cited
By later US patents
- Method and circuitry for minimizing clock-data skew in a bus system385US 5,432,823 ARambus Inc. · 1995
- Configurable processor system unit214US 6,467,009 B1Triscend Corporation · 2002
- Apparatus and method for controlling a master/slave system via master device synchronization192US 6,839,393 B1Rambus Inc. · 2005
- On-chip bus architecture that is both processor independent and scalable149US 6,122,690 AMentor Graphics Corporation · 2000
- High speed parallel bus and data transfer method147US 4,570,220 AIntel Corporation · 1986