Method and circuitry for minimizing clock-data skew in a bus system

A synchronous bus system for minimizing clock-data skew, the bus system comprising:

• a) a data bus having a first end and a second end;
• b) a clockline carrying a clock signal, the clockline having:
• i) a first clockline segment extending from the first end of the data bus to a turnaround near the second end of the data bus;
• ii) a second clockline segment extending from the turnaround to the first end of the data bus;
• and
• c) a first device coupled to the data bus for transmitting data to a second device, including synchronization circuitry, the synchronization circuitry synchronizing a data signal and the clock signal on a transmit clockline segment, the second device having the transmit clockline segment, the transmit clockline segment being a selected one of the first and second clockline segments, the synchronization circuitry including:
• i) a phase comparator for comparing a receive clock input to a transmit clock input to generate a select signal, the transmit clock input being the transmit clockline segment;
• ii) a delay element coupled to the data signal and outputting a delayed data signal;
• iii) a multiplexer for selecting between the data signal and the delayed data signal in response to the select signal, the multiplexer having a mux output;
• and
• iv) a latch having an input coupled to the mux output, the latch having an enable input coupled to the transmit clock input, and an output outputting a second data signal aligned with the transmit clock input.

A synchronous bus system for minimizing clock-data skew, the bus system comprising:

• a) a data bus having a first end and a second end;
• b) a clockline carrying a clock signal, the clockline having:
• i) a first clockline segment extending from the first end of the data bus to a turnaround near the second end of the data bus;
• ii) a second clockline segment extending from the turnaround to the first end of the data bus;
• and
• c) synchronization circuitry for synchronizing a multiplicity of data signals with the clock signal on a transmit clockline segment and for sending the multiplicity of data signals to the data bus, the transmit clockline segment being a selected one of the first and second clockline segments, the synchronization circuitry including:
• i) a phase comparator for comparing a receive clock input to a transmit clock input to generate a select signal, the transmit clock input being the transmit clockline segment;
• ii) a delay element coupled to a first control signal and outputting a delayed first control signal;
• iii) a multiplexer for selecting between the first control signal and the delayed first control in response to the select signal, the multiplexer having a mux output;
• iv) a first latch having an input coupled to the mux output, the latch having an enable input coupled to the transmit clock input, and an output outputting a second control signal aligned with the transmit clock input;
• v) a second latch having a multiplicity of inputs coupled to the multiplicity of data signal and having an enable input coupled to a third control signal, and having a multiplicity of second latch outputs;
• vi) a third latch having a multiplicity of inputs coupled to the multiplicity of second latch outputs, and having an enable input coupled to the second control signal and a multiplicity of third latch outputs coupled to data bus.

A synchronous system operable without framing signals for minimizing clock-data skew comprising:

• a) a single independent clock source generating a clock;
• b) a single clockline carrying the clock signal, the clockline including:
• i) a first clockline segment having a first end, and a second end, the first end being coupled to the clock source;
• ii) a turnaround coupled to the second end of the first clockline segment;
• iii) a second clockline segment having a first end and a second end, the first end being coupled to the turnaround;
• c) a data bus having a first end and a second end, the data bus extending from the first end of the first clockline segment to the second end of the first clockline segment, the data bus carrying a first data signal, the first data signal propagating on the data bus contemporaneously and in a constant phase relationship with the clock signal traveling on the first clockline segment;
• d) a first device comprising a first circuit for transmitting the first data signal to the data bus upon arrival at the first device of the clock signal on the first clockline segment;
• and
• e) a second device copying a second circuit for receiving the first data signal on the data bus upon arrival at the second device of the clock signal on the first clockline segment, said second circuit transmitting second data signal to the data bus upon arrival of the clock signal on the second clockline segment, the second data signal traveling on the data bus contemporaneously and in a constant phase relationship with the clock signal traveling on the second clockline segment.

A method for minimizing clock-data skew in a synchronous bus system operable without framing signals, the synchronous bus system having devices coupled to a data bus and a clockline, the data bus having a first end and a second end, the clockline having a first clockline segment extending from the first end of the data bus to a turnaround near the second end of the data bus and a second clockline segment extending from the turnaround to the first end of the data bus, and a single independent clock coupling a clock signal to the first end of the first clockline segment, the method comprising the steps of:

• a) transmitting a first data signal to the data bus by a first device upon arrival of the clock signal on the first clockline segment at the first device, the first data signal traveling on the data bus in a same direction as the clock signal on the first clockline segment, the first data signal traveling on the data bus contemporaneously and in a constant phase relationship with the clock signal traveling on the first clockline segment;
• b) receiving at a second device the first data signal from the data bus upon arrival at the second device of the clock signal on the first clockline segment, the second device being coupled to the first clockline segment;
• and
• c) transmitting a second data signal from the second device to the data bus upon arrival of the clock signal on the second clockline segment at the second device, the second data signal traveling on the data bus in a same direction as the clock signal on the second clockline segment, the second data signal traveling on the data bus contemporaneously and in a constant phase relationship with the clock signal traveling on the second clockline segment.

A method for minimizing skew in a synchronous bus system, said system comprising a clock line and a data bus, said clockline having a first clockline segment and a second clockline segment, said first clockline segment having a first end coupled to a clock source and a second end coupled to a turnaround, said second clockline segment having a first end and a second end, said first end coupled to the turnaround, said data base having a first end and a second end, said data bus extending from the first end of the first clockline segment to the second end of the first clockline segment, said method comprising the steps of:

• coupling a first device to the data bus and the first and second clockline segments;
• coupling a second device to the data bus and the first and second clockline segments, said second device coupled near the turnaround;
• if a first data signal is to be transmitted from the first device to the second device;
• transmitting the first data signal to the data bus by the first device upon arrival of a clock signal on the first clockline segment at the first device, the first data signal traveling on the data bus in a same direction as the clock signal on the first clockline segment, and
• receiving the first data signal at the second device from the data bus upon arrival of the clock signal on the first clockline segment;
• and
• if a second data signal is to be transmitted from the second device to the first device;
• transmitting the second data signal to the data bus by the second device upon arrival of a clock signal on the second clockline segment at the second device, the second data signal traveling on the data bus in a same direction as the clock signal on the second clockline segment, and
• receiving the second data signal at the first device from the data bus upon arrival of the clock signal on the second clockline segment.

A synchronous system operable without framing signals for minimizing clock-data skew comprising:

• a) a single independent clock source generating a clock;
• b) a single clockline carrying the clock signal, the clockline including:
• i) a first clockline segment having a first end and a second end, the first end being coupled to the clock source;
• ii) a turnaround coupled to the second end of the first clockline segment;
• iii) a second clockline segment having a first end and a second end, the first end being coupled to the turnaround;
• c) a data bus having a first end and a second end, the data bus extending from the first end of the first clockline segment to the second end of the first clockline segment, the data bus carrying a first data signal, the first data signal propagating on the data bus contemporaneously and in a constant phase relationship with the clock signal traveling on the second clockline segment;
• d) a first device comprising a first circuit for transmitting the first data signal to the data bus upon arrival at the first device of the clock signal on the second clockline segment;
• and
• e) a second device comprising a second circuit for receiving the first data signal on the data bus upon arrival at the second device of the clock signal on the second clockline segment, said second circuit transmitting a second data signal to the data bus upon arrival of the clock signal on the first clockline segment, the second data signal traveling on the data bus contemporaneously and in a constant phase relationship with the clock signal traveling on the first clockline segment.

A method for minimizing clock-data skew in a synchronous bus system operable without framing signals, the synchronous bus system having devices coupled to a data bus and a clockline, the data bus having a first end and a second end, the clockline having a first clockline segment extending from the first end of the data bus to a turnaround near the second end of the data bus and a second clockline segment extending from the turnaround to the first end of the data bus, and a single independent clock coupling a clock signal to the first end of the first clockline segment, the method comprising the steps of:

• a) transmitting a first data signal to the data bus by a first device upon arrival of the clock signal on the second clockline segment at the first device, the first data signal traveling on the data bus in a same direction as the clock signal on the second clockline segment, the first data signal traveling on the data bus contemporaneously and in a constant phase relationship with the clock signal traveling on the second clockline segment;
• b) receiving at a second device the first data signal from the data bus upon arrival at the second device of the clock signal on the second clockline segment, the second device being coupled to the second clockline segment;
• and
• c) transmitting a second data signal from the second device to the data bus upon arrival of the clock signal on the first clockline segment at the second device, the second data signal traveling on the data bus in a same direction as the clock signal on the first clockline segment, the second data signal traveling on the data bus contemporaneously and in a constant phase relationship with the clock signal traveling on the first clockline segment.