Clock-to-data synchronization
AssigneeNVIDIA Corporation
InventorsOfek Abadi, Omer Wolkovitz
Life of this patent
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Abstract
Technology related to calibrating synchronization of a data signal to a forwarded clock signal is described. A circuit includes a receiver circuit and a clock-to-data synchronization circuit. The receiver circuit receives a data signal and includes two inverters and two resistors. The clock-to-data synchronization circuit receives the data signal and the clock signal and determines an indication of synchronization between the data and clock signals. The clock-to-data synchronization circuit adjusts, using the indication, a parameter of the receiver circuit to synchronize the data signal and the clock signal.
Claims20
A circuit comprising:
- a receiver circuit configured to receive a data signal, the receiver circuit comprising a first inverter, a second inverter coupled in series to the first inverter, a first feedback resistor coupled between an input of the first inverter and an output of the second inverter, and a second feedback resistor coupled between the input of the first inverter and an input of the second inverter;
- and
- a clock-to-data synchronization circuit configured to receive the data signal and a clock signal, wherein the clock-to-data synchronization circuit is configured to determine an indication of synchronization between the data signal and the clock signal and adjust, using the indication, a parameter of the receiver circuit to synchronize the data signal and the clock signal.
A communication device comprising:
- a receiver comprising:
- a first inverter comprising an input to receive a data signal;
- and
- a first resistor coupled in parallel to the first inverter;
- peak detection logic configured to receive a clock signal;
- a comparator comprising a first input coupled to the input of the first inverter and a second input coupled to the peak detection logic;
- memory;
- and
- a controller operatively coupled to the memory, wherein upon executing instructions stored within the memory, the controller is configured to:
- receive a first indication from the comparator based on a first voltage level received at the first input of the comparator and a second voltage level received at the second input of the comparator;
- and
- cause, based on the first indication, at least one of a first resistance of the first resistor or a first on-resistance of the first inverter to be adjusted.
A method comprising:
- receiving, by a receiver circuit, a first peak voltage corresponding to a data signal, wherein the receiver circuit comprises a first inverter, a second inverter coupled in series to the first inverter, a first feedback resistor coupled between an input of the first inverter and an output of the second inverter, and a second feedback resistor coupled between the input of the first inverter and an input of the second inverter;
- determining, by peak detection logic, a second peak voltage corresponding to a clock signal;
- receiving, by a comparator, the first and second peak voltages, wherein the comparator is configured to output an indication of synchronization between the data signal and the clock signal;
- and
- adjusting, using the indication, a parameter of the receiver circuit to synchronize the data signal and the clock signal.
Dependencies are inferred from the claim text.