System-on-chip and an interconnect bus included in the system on chip

A system-on-chip comprising:

• a first slave device having a first slave automotive safety integrity level (ASIL), the first slave device including a first address region having the first slave ASIL and a second address region having a second slave ASIL being higher than the first slave ASIL;
• a first master device configured to output a first access request for the first slave device, the first master device having a first mater ASIL being lower than the first slave ASIL;
• a second master device configured to output a second access request for the second address region of the first slave device, the second master device having a second master ASIL being lower than the second slave ASIL and being equal to or higher than the first slave level;
• an interconnect bus configured to
• receive the first access request from the first master device,
• block the first access request in response to a case in which the first master safety ASIL is lower than the first salve ASIL,
• receive the second access request from the second master device, and
• output the second access request in response to a case in which the second master ASIL is equal to or higher than the first slave level;
• a safety memory protecting unit configured to:
• receive the first access request from the interconnect bus, and
• block the second access request in response to a case in which the second master ASIL is lower than the second slave ASIL.

An operation of a system-on-chip including a first master device, an interconnect bus, a safety memory protecting unit, and a first slave device, the method comprising:

• providing, by the first master device having a first master automotive safety integrity level (ASIL), a first access request for a first address region of the first slave device, the first slave device having a first slave ASIL, and the first address region having a second slave ASIL;
• transferring, by the interconnect bus, the first access request to the safety memory protecting unit in response to a case in which the first master ASIL is equal to or higher than the first slave ASIL of the first slave device;
• and
• blocking, by the safety memory protecting unit, the first access request in response to a case in which the first maser ASIL is lower than the second slave ASIL of the first address region.