US 4,570,220 AGranted

High speed parallel bus and data transfer method

AssigneeIntel Corporation

InventorsRaymond S. Tetrick, John Beaston, Robert L. Farrell, Alireza Sarabi, Sudarshan Balachandran, Edwin L. Jacks, Jr., Steven D. Kassel

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Abstract

A multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources. The bus structure of the present invention includes both a parallel and serial bus which interconnects data processing units and peripheral devices (collectively referred to as "agents") to permit the exchange of data and messages at high speed using a minimum of "handshake" events prior to the actual data transfer. Both the serial and parallel bus protocals are controlled by message control means coupled to each communicating agent. A local bus is coupled to processing agents within the system such that local memory and secondary processing resources may be accessed without impacting data traffic along the parallel bus. Direct access to resources coupled to the local bus of an agent from other bus agents is also controlled by the message control means.

Claims21

Dependent claims

A high speed parallel bus structure for transferring data between a plurality of data processing devices ("agents"), comprising:

address data lines for transmitting address and data information between said agents;
command lines for transmitting commands from a requesting agent to a replying agent, such that said requesting agent may transmit a requester ready (REQ RDY) signal to said replying agent notifying said replying agent that said requestor is ready to proceed with the data operation identified by said command, and a replier ready signal (REPLY RDY) transmitted by said replying agent on said command lines notifying said requesting agent that said replying agent is prepared to proceed with said data operation;
said command lines being reallocated between said requesting and replying agents once said command has been transmitted, thereby permitting the transmission of said REQ RDY and REPLY RDY signals;
said data to be transferred being considered valid only upon the assertion of both said REQ RDY and REPLY RDY signals;
message control means coupled to each of said agents in said bus structure for coupling said agents to said parallel bus;
said message control means further including arbitration means for allocating the use of said parallel bus between agents;
whereby data is transferred between agents at high speed.

4 more elements

Dependencies are inferred from the claim text.