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AssigneeMentor Graphics Corporation
InventorsGianni Michele Nannetti, Tirumal Rao Parvataneni
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A bus in an integrated circuit uses bus interfaces to couple functional blocks to the bus in a processor independent and scalable manner. Various embodiments of the bus interfaces include a bus interface for a bus master functional block, a bus interface for a slave functional block, and a bus interface for either a bus master functional block or a slave functional block. Each bus interface includes a state machine that has at least two operational modes including a fast operational mode having two states and a normal operational mode having at least four states. A bus interface coupled to a bus master functional block implements an operational mode and a bus interface coupled to a slave functional block operates in a complementary operational mode. Each bus interface is also equipped to facilitate scaling of the address and/or data width on the bus. Various embodiments of the bus interfaces are also equipped to support multiple bus masters, broadcast writes, burst mode transfers, and/or tri-states on the bus.
An integrated circuit comprising a bus, a first bus master function block coupled to the bus, and a slave function block also coupled to the bus, the first bus master function block having a bus master interface including a state machine that conducts a bus transaction between the first bus master function block and the bus slave function block in either a two state fast mode of operation, or an at least four state normal mode of operation, wherein the at least four states of the at least four state normal mode of operation includes the two states of the two state fast mode of operation.
An integrated circuit comprising a bus, a first bus master function block coupled to the bus, and a bus slave function block also coupled to the bus, the bus slave function block having a bus slave interface including a state machine that conducts a bus transaction between the first bus master function block and the bus slave function block in either a two state fast mode of operation, or an at least four state normal mode of operation, wherein the four states of the at least four state normal mode of operation includes the two states of the two state fast mode of operation.
An integrated circuit comprising a bus, a bus master/slave function block coupled to the bus, and either a bus master or a bus slave function block also coupled to the bus, the bus master/slave function block having a bus master/slave interface including a state machine that conducts a bus transaction with the bus master or slave function block as a bus master if the bus master or slave function block is a bus slave function block or as a bus slave if the bus master or slave function block is a bus master function block, the bus transaction being conducted in either a two state fast mode of operation, or an at least four state normal mode of operation, wherein the four states of the at least four state normal mode of operation includes the two states of the two state fast mode of operation.
An integrated circuit comprising:
The integrated circuit of 30;
The integrated circuit of 30;
Dependencies are inferred from the claim text.