US 12,248,422 B2 · Systems and methods for lane management in a communication bus

Abstract

Systems and method for lane management in a communication bus are disclosed. In one aspects, a communication link or bus between a baseband processor (BBP) and a radio frequency integrated circuit (RFIC) may include multiple uplink lanes for transmission and multiple downlink lanes for reception that are frequency constrained and adjust bandwidth by adjusting duty cycles on the lanes. To reduce power consumption by the communication bus, exemplary aspects of the present disclosure contemplate using in-band signaling to turn off lanes selectively during inactive periods such that the lanes do not duty cycle in tandem with active lanes. Additionally, in some aspects, the uplink lanes may be continuously active during transmission while the downlink lanes are turned off. This dynamic lane usage reduces power consumption, does not require additional pins for sideband signaling, and does not introduce any additional latency.

Claims20

Dependent claims

A baseband processor (BBP) comprising:

a bus interface configured to couple to a communication bus, the bus interface comprising:
one or more uplink lanes;
and
one or more downlink lanes;
and
a control circuit coupled to the bus interface and configured to:
adjust a bandwidth for the communication bus by changing a duty cycle associated with the communication bus;
and
while the communication bus is active:
cycle the one or more downlink lanes on and off during a receive slot;
and
turn on at least one of the one or more uplink lanes on during an entirety of a transmit slot.

9 more elements

Dependencies are inferred from the claim text.

Systems and methods for lane management in a communication bus

Life of this patent

Systems and methods for lane management in a communication bus

Life of this patent

Abstract

Claims20