G06F 12/0879
Burst mode
G06F12/0879 (Burst mode) appears on 266 US grants and 196 published applications in this corpus.
Search patents in G06F- Granted patents
- 266
- Published applications
- 196
- Assignees
- 98
- Inventors
- 528
- Latest grant
- 26 May 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1989 | 2 | 0 |
| 1990 | 2 | 0 |
| 1991 | 2 | 0 |
| 1992 | 2 | 0 |
| 1993 | 2 | 0 |
| 1994 | 4 | 0 |
| 1995 | 8 | 0 |
| 1996 | 7 | 0 |
| 1997 | 9 | 0 |
| 1998 | 15 | 0 |
| 1999 | 15 | 0 |
| 2000 | 8 | 0 |
| 2001 | 8 | 4 |
| 2002 | 11 | 22 |
| 2003 | 5 | 6 |
| 2004 | 17 | 5 |
| 2005 | 6 | 6 |
| 2006 | 6 | 8 |
| 2007 | 6 | 2 |
| 2008 | 6 | 5 |
| 2009 | 3 | 4 |
| 2010 | 2 | 4 |
| 2011 | 2 | 4 |
| 2012 | 2 | 3 |
| 2013 | 5 | 4 |
| 2014 | 2 | 2 |
| 2015 | 4 | 7 |
| 2016 | 7 | 6 |
| 2017 | 7 | 7 |
| 2018 | 11 | 8 |
| 2019 | 8 | 11 |
| 2020 | 6 | 13 |
| 2021 | 8 | 14 |
| 2022 | 12 | 16 |
| 2023 | 17 | 17 |
| 2024 | 14 | 8 |
| 2025 | 12 | 5 |
| 2026 | 3 | 5 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Memory controller having a write buffers26 May 2026US 12,638,978 B2NXP USA, Inc.
- Error correcting codes for multi-master memory controller10 Mar 2026US 12,572,416 B2Texas Instruments Incorporated
- Cache writeback circuit13 Jan 2026US 12,524,344 B1Apple Inc.
- Method and device for rapidly searching cache30 Dec 2025US 12,511,238 B2Shanghai Zhaoxin Semiconductor Co., Ltd.
- Handling non-correctable errors29 Jul 2025US 12,373,286 B2Texas Instruments Incorporated
- Method for processing memory commands in computing system2 Jul 2026US 2026/0186971 A1Mediatek Inc.
- Write burst gathering across multiple streams30 Apr 2026US 2026/0119387 A1Arm Limited
- Memory controller having a write buffers19 Mar 2026US 2026/0079622 A1NXP USA, Inc.
- Split-entry dram cache5 Mar 2026US 2026/0064597 A1Rambus Inc.
- Atomic handling for disaggregated 3d structured socs15 Jan 2026US 2026/0017202 A1Intel Corporation
Most cited
By later US patents
- Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus96US 5,228,134 AIntel Corporation · 1993
- High speed burst read address generation with high speed transfer91US 5,345,573 ABull HN Information Systems Inc. · 1994
- Active cache for a microprocessor80US 5,608,892 AAlantec Corporation · 1997
- High speed flexible slave interface for parallel common bus to local cache buffer70US 5,761,707 ASun Microsystems, Inc. · 1998
- Programmable burst data transfer apparatus and technique69US 5,134,699 AAdvanced Micro Devices, Inc. · 1992