US 5,228,134 AGranted

Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus

AssigneeIntel Corporation

InventorsPeter D. MacWilliams, Clair C. Webb, Robert L. Farrell

Life of this patent

Estimating the term…

Loading patent…

Abstract

An integrated circuit implements a cache static random access memory (SRAM) storage element which includes a central processor unit (CPU) bus interface incorporating multiplexers and buffers circuits for optimizing burst read and write operations across the CPU bus. Theses circuits allow a full cache line to be read/written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.

Claims27

Dependent claims

An integrated circuit cache memory for temporarily holding data in a computer system, the computer system comprising a central processing unit (CPU) with a CPU clock signal, a prescribed burst order, an associated CPU bus coupled to the CPU and operating synchronous to the CPU clock signal, and a main memory with an associated memory bus coupled to the main memory, the integrated circuit cache memory comprising:

(a) a cache storage array having a prescribed cache line width;
(b) a CPU bus interface coupled to the CPU bus and said cache storage array, said CPU bus interface comprising:
(i) CPU buffer means coupled to the CPU bus and said cache storage array for optimizing burst read and write operations on the CPU bus and for accessing a full cache line of said cache storage array with a single access;
and
(ii) a CPU bus interface controller for controlling transfers to and from the CPU bus and to and from said cache storage array including control of burst transfers in the prescribed CPU order;
(c) a memory bus interface coupled to the memory bus and said cache storage array, said memory bus interface comprising:
(i) a plurality of cache line wide memory bus buffers for buffering of data to or from the memory bus, and to or from said cache storage array, including memory bus reads, write-throughs, write-backs and snoops;
and
(ii) a memory bus interface controller for selecting which of said plurality of memory bus buffers is to be used during a particular memory bus cycle;
and
(d) a data path means coupled to said CPU bus interface and memory bus interface for transferring data directly between said CPU bus interface and said memory bus interface.

8 more elements

An integrated cache memory circuit coupled to a memory bus and a CPU bus, said circuit comprising:

(a) a cache storage array;
(b) a memory port coupled to the memory bus;
(c) a CPU port coupled to the CPU bus;
(d) a plurality of cache line wide buffers for supporting concurrent operations at said memory port and said CPU port, each of said cache line wide buffers having a full cache line wide interface to said cache storage array;
(e) an internal bus means for accessing said cache storage array from said memory port and said CPU port, said internal bus means comprising a connection bus which supports transfers between the CPU bus and the memory bus without involving said cache storage array while array accesses are occurring;
(f) memory port control means for selecting which of said plurality of cache line wide memory port buffers is to be used during a particular memory bus access;
and
(g) CPU port control means for addressing said cache storage array and for selecting which of said plurality of cache line wide CPU port buffers is to be written to during an access to said array.

5 more elements

An integrated cache memory circuit providing a gateway between a CPU bus and a memory bus in a microprocessor computer system comprising:

(a) a random-access cache storage array organized as a multi-way, set associative cache;
(b) a CPU bus interface, also comprising a cache line wide CPU interface buffer for providing access to said cache storage array from the CPU bus;
(c) a memory bus interface providing access to said cache storage array from the memory bus, said memory bus also comprising including a plurality of memory bus buffers;
(d) a bus providing a bypass path between said CPU bus interface and said memory bus interface independent of accesses involving said cache storage array, wherein each of said plurality of memory bus buffers and said CPU interface buffer has a full cache line wide interface to said cache storage array to support concurrent operations at said CPU interface and said memory bus interface;
and
(e) data transfer control means for independent, asynchronous control of data transfer that is occurring at said CPU bus interface and said memory bus interface.

3 more elements

Dependencies are inferred from the claim text.