Memory controller having a write buffers

In a non-volatile memory (NVM) controller configured to control reads from and write to an NVM array, a method comprises:

• storing each received write access request to the NVM array into a write buffer having a plurality of entries, each entry configured to store a write access having a corresponding page address of the NVM array and corresponding write data;
• initiating a burst write from the write buffer to the NVM array by selecting a valid entry with a lowest page address as a first valid entry from the write buffer and sending a first write beat of the burst write for the first valid entry to the NVM array, wherein the length of the burst write is undefined upon sending the first write beat of the burst write;
• continuing the burst write from the write buffer to the NVM array by selecting a next valid entry from the write buffer whose corresponding page address is immediately consecutive to a corresponding page address of an immediately previously sent write beat of the burst write and sending a next write beat of the burst write for the next valid entry to the NVM array;
• and
• closing the burst write, wherein the length of the burst write is defined upon closing the burst write.

A non-volatile memory (NVM) controller configured to control reads from and writes to an NVM array, the NVM controller comprising:

• a write buffer having a plurality of entries, each entry configured to store a write access having a corresponding page address of the NVM array and corresponding write data;
• and
• a buffer control circuit configured to:
• store write accesses into the write buffer based on received write access requests, and
• generate burst writes from the write buffer to the NVM array, wherein the buffer control circuit generates a burst write by initiating the burst write by selecting a valid entry with a lowest page address as a first valid entry from the write buffer, sending a first write beat for the write access of the first valid entry to the NVM array, and sequentially selecting write accesses from the write buffer which have consecutive page addresses, wherein the length of the burst write is undefined when the burst write to the NVM array is initiated.