G06F 12/0877
Cache access modes
G06F12/0877 (Cache access modes) appears on 1,899 US grants and 1,877 published applications in this corpus.
Search patents in G06F- Granted patents
- 1,899
- Published applications
- 1,877
- Assignees
- 333
- Inventors
- 3,432
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1979 | 1 | 0 |
| 1980 | 4 | 0 |
| 1981 | 0 | 0 |
| 1982 | 2 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 1 | 0 |
| 1987 | 1 | 0 |
| 1988 | 4 | 0 |
| 1989 | 6 | 0 |
| 1990 | 2 | 0 |
| 1991 | 7 | 0 |
| 1992 | 7 | 0 |
| 1993 | 10 | 0 |
| 1994 | 12 | 0 |
| 1995 | 14 | 0 |
| 1996 | 19 | 0 |
| 1997 | 23 | 0 |
| 1998 | 30 | 0 |
| 1999 | 23 | 0 |
| 2000 | 24 | 0 |
| 2001 | 22 | 9 |
| 2002 | 26 | 32 |
| 2003 | 19 | 14 |
| 2004 | 29 | 31 |
| 2005 | 16 | 25 |
| 2006 | 18 | 25 |
| 2007 | 23 | 21 |
| 2008 | 26 | 26 |
| 2009 | 23 | 27 |
| 2010 | 12 | 20 |
| 2011 | 21 | 20 |
| 2012 | 24 | 30 |
| 2013 | 27 | 32 |
| 2014 | 33 | 36 |
| 2015 | 45 | 60 |
| 2016 | 66 | 61 |
| 2017 | 53 | 52 |
| 2018 | 58 | 62 |
| 2019 | 65 | 93 |
| 2020 | 77 | 203 |
| 2021 | 156 | 242 |
| 2022 | 218 | 241 |
| 2023 | 234 | 174 |
| 2024 | 189 | 162 |
| 2025 | 158 | 123 |
| 2026 | 71 | 56 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Cache structure and utilization6 Oct 2026US 12,754,876 B2Intel Corporation
- Memory access statistics monitoring22 Sep 2026US 12,743,370 B2Micron Technology, Inc.
- Caching a memory descriptor for plural input/output requests22 Sep 2026US 12,743,380 B2Microsoft Technology Licensing, LLC
- System, apparatus, non-transitory computer readable medium, and method of storing an embedding table15 Sep 2026US 12,737,290 B2Samsung Electronics Co., Ltd.
- Systems and methods for updating memory side caches in a multi-GPU configuration15 Sep 2026US 12,737,317 B2Intel Corporation
- Handling parity data during data folding in a memory device8 Oct 2026US 2026/0310550 A1
- Dynamic allocation of a last level cache (llc) to a feature in a head-mounted display (hmd)8 Oct 2026US 2026/0310607 A1QUALCOMM Incorporated
- Data storage device for managing page status information, operating method of the data storage device, and memory controller for the data storage device1 Oct 2026US 2026/0300161 A1SK hynix Inc.
- Methods and apparatus for eviction in dual datapath victim cache system1 Oct 2026US 2026/0300187 A1
- Techniques for a fragment cursor24 Sep 2026US 2026/0288633 A1Micron Technology, Inc.
Most cited
By later US patents
- Write-back cache protection398US 8,327,080 B1EMC Corporation · 2012
- Product for global updating modified data object represented in concatenated multiple virtual space by segment mapping203US 5,687,343 AInternational Business Machines Corporation · 1997
- Triple port cache memory143US 5,442,770 ANEC Electronics Corporation · 1995
- Method to control I/O accesses in a multi-tasking virtual memory virtual machine type data processing system126US 4,742,447 AInternational Business Machines Corporation · 1988
- Partial cache line write transactions in a computing system with a write back cache123US 5,586,297 AHewlett-Packard Company · 1996