G06F 12/0884
Parallel mode
Official title: Parallel mode, e.g. in parallel with main memory or CPU
G06F12/0884 (Parallel mode) appears on 171 US grants and 170 published applications in this corpus.
Search patents in G06F- Granted patents
- 171
- Published applications
- 170
- Assignees
- 68
- Inventors
- 310
- Latest grant
- 15 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1979 | 1 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 2 | 0 |
| 1990 | 0 | 0 |
| 1991 | 1 | 0 |
| 1992 | 1 | 0 |
| 1993 | 5 | 0 |
| 1994 | 3 | 0 |
| 1995 | 1 | 0 |
| 1996 | 1 | 0 |
| 1997 | 1 | 0 |
| 1998 | 3 | 0 |
| 1999 | 3 | 0 |
| 2000 | 4 | 0 |
| 2001 | 4 | 1 |
| 2002 | 1 | 3 |
| 2003 | 2 | 1 |
| 2004 | 0 | 1 |
| 2005 | 2 | 2 |
| 2006 | 2 | 2 |
| 2007 | 1 | 1 |
| 2008 | 2 | 1 |
| 2009 | 3 | 3 |
| 2010 | 0 | 0 |
| 2011 | 0 | 2 |
| 2012 | 3 | 1 |
| 2013 | 1 | 5 |
| 2014 | 3 | 4 |
| 2015 | 5 | 8 |
| 2016 | 7 | 6 |
| 2017 | 5 | 4 |
| 2018 | 5 | 8 |
| 2019 | 6 | 14 |
| 2020 | 12 | 27 |
| 2021 | 10 | 9 |
| 2022 | 14 | 8 |
| 2023 | 15 | 14 |
| 2024 | 17 | 19 |
| 2025 | 17 | 20 |
| 2026 | 6 | 6 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- System, apparatus, non-transitory computer readable medium, and method of storing an embedding table15 Sep 2026US 12,737,290 B2Samsung Electronics Co., Ltd.
- Methods and apparatus for eviction in dual datapath victim cache system16 Jun 2026US 12,657,134 B2Texas Instruments Incorporated
- Methods and apparatus for inflight data forwarding and invalidation of pending writes in store queue16 Jun 2026US 12,657,135 B2Texas Instruments Incorporated
- Methods and apparatus to facilitate read-modify-write support in a victim cache12 May 2026US 12,625,822 B2Texas Instruments Incorporated
- Caching in a solver system10 Mar 2026US 12,572,470 B1Amazon Technologies, Inc.
- Methods and apparatus for eviction in dual datapath victim cache system1 Oct 2026US 2026/0300187 A1
- Methods and apparatus to facilitate read-modify-write support in a victim cache17 Sep 2026US 2026/0277825 A1
- System, apparatus, non-transitory computer readable medium, and method of storing an embedding table9 Jul 2026US 2026/0195266 A1Samsung Electronics Co., Ltd.
- Caching in a solver system2 Apr 2026US 2026/0093625 A1Amazon Technologies, Inc.
- Victim cache that supports draining write-miss entries5 Feb 2026US 2026/0037451 A1
Most cited
By later US patents
- Main memory access in a microprocessor system with a cache memory76US 4,847,758 AZenith Electronics Corporation · 1989
- Controller for two-way set associative cache67US 5,210,845 AIntel Corporation · 1993
- Cache memory command buffer circuit60US 4,354,232 AHoneywell Information Systems Inc. · 1982
- Private cache-to-CPU interface in a bus oriented data processing system55US 4,161,024 AHoneywell Information Systems Inc. · 1979
- Integrated level two cache and controller with multiple ports, L1 bypass and concurrent accessing51US 6,226,722 B1International Business Machines Corporation · 2001