US 6,226,722 B1 · Integrated level two cache and controller with multiple ports, L1 bypass and concurrent accessing

Abstract

A memory system wherein data retrieval is simultaneously initiated in both and L2 cache and main memory, which allows memory latency associated with arbitration, memory DRAM address translation, and the like to be minimized in the event that the data sought by the processor is not in the L2 cache (miss). The invention allows for any memory access to be interrupted in the storage control unit prior to any memory signals being activated. The L2 and memory access controls are in a single component, i.e. the storage control unit (SCU). Both the L2 and the memory have a unique port into the CPU which allows data to be directly transferred. This eliminates the overhead associated with storing the data in an intermediate device, such as a cache or memory controller.

Claims20

Dependent claims

A computer system including a processing unit, L2 cache and memory, comprising:

a storage control unit including an integrated cache controller and memory controller for controlling operations of said L2 cache and said memory, respectively;
means for simultaneously initiating a first operation to retrieve information from said L2 cache and a second operation to retrieve information from said memory;
means for determining if information required by said processing unit is stored in said L2 cache;
and
means for aborting said second operation by providing a stop memory operation signal directly from said cache controller to said memory controller concurrent with a determination that said information is in said L2 cache;
wherein said second operation is aborted before any request signals are output to said memory and said memory continues operations independent of said second operation.

3 more elements

Dependencies are inferred from the claim text.

Integrated level two cache and controller with multiple ports, L1 bypass and concurrent accessing

Life of this patent

Integrated level two cache and controller with multiple ports, L1 bypass and concurrent accessing

Life of this patent

Abstract

Claims20