Main memory access in a microprocessor system with a cache memory

In a data processing system having a processing unit for reading and processing desired data either from a fast cache memory wherein first data most frequently processed by said processing unit is stored or from a slower main memory including a plurality of matrix memories wherein second data less frequently processed by said processing unit than said first data is stored, and wherein either said cache memory or said main memory is accessed by said processing unit during a plurality of successive system operating cycles, a method of accessing said main memory comprising:

• initiating access of said main memory by asserting a precharging signal to said main memory over a predetermined time interval in preparation for accessing said main memory;
• accessing said cache memory during said predetermined time interval;
• accessing said main memory following said predetermined time interval when said cache memory does not have the desired data and reading the desired data from said main memory;
• accessing said main memory in a paged manner when the desired data for successive system operating cycles is in only one of the matrix memories;
• and
• providing each of said matrix memories with a plurality of addressable memory locations arranged in a matrix array and defining each of said addressable memory locations by a given row and column and providing said precharging signal as a Column Address Strobe (CAS) signal.

In a data processing system having a processing unit for reading and processing desired data either from a fast cache memory wherein first data most frequently processed by said processing unit is stored or from a slower main memory wherein second data less frequently processed by said processing unit than said first data is stored, and wherein either said cache memory or said main memory is accessed by said processing unit during a plurality of successive system operating cycles, a method of accessing said main memory comprising:

• initiating access of said main memory by asserting a precharging signal to said main memory over a predetermined time interval in preparation for accessing said main memory;
• accessing said cache memory during said predetermined time interval;
• accessing said main memory in a paged manner following said predetermined time interval when said cache memory does not have the desired data and reading the desired data from said main memory;
• and
• providing said main memory with a plurality of matrix memories each having a plurality of addressable memory locations arranged in a matrix array and defining each of said addressable memory locations by a given row and column and providing said precharging signal as a Row Address Strobe (RAS) signal when said matrix memories are accessed in a non-paged manner.