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US 2026/0037451 A1Published application
Victim cache that supports draining write-miss entries
OwnerNaveen BHORIA, Timothy David ANDERSON +1inventors
InventorsNaveen BHORIA, Timothy David ANDERSON, Pete HIPPLEHEUSER
Life of this patent
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Abstract
A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.
Claims20
A device, comprising:
- a processor;
- a cache memory including:
- a cache line configurable to store an entry;
- and
- a value indicating whether the entry stored in the cache line is a write-miss entry;
- and
- an interface configurable to couple the cache memory with the processor;
- and
- a controller configurable to:
- determine whether the interface is in an idle state;
- and
- based on a determination that the interface is in the idle state, evict the cache line based on the value indicating that the entry stored in the cache line is a write-miss entry.
9 more elements
A method, comprising:
- storing data in a cache line of a cache memory;
- storing a value in the cache memory that indicates whether the data is associated with a write-miss entry;
- determining whether an interface of the cache memory is in an idle state;
- and
- based on determining that the interface is in the idle state, evicting the data from the cache line based on the value indicating that the data is associated with a write-miss entry.
2 more elements
Dependencies are inferred from the claim text.