Cache memory command buffer circuit

In a computer system which includes a central processing unit (CPU), a high-speed cache memory unit, and a system interface unit (SIU) for controlling command and data transfer between a lower speed main memory and either said CPU or said cache memory unit, a cache memory command buffer circuit for allowing said cache memory unit and said SIU to operate independent of each other and for ensuring that commands to said cache memory unit and to SIU are executed in proper sequence, said cache memory command buffer circuit comprising:

• a read buffer for storing read signals from said CPU to said cache memory unit or to said SIU, said read signals including command, data, and address signals;
• a write buffer for storing write signals from said CPU to said cache memory unit or to said SIU, said read signals including command, data, and address signals;
• and
• a sequence control circuit connected to said read and write buffers and receiving signals from said CPU, said SIU, and said cache memory, said sequence control circuit including means for storing said read signals from said CPU in said read buffer and said write signals from said CPU in said write buffer and for outputting said read and write signals to said cache memory unit and to said SIU in the proper sequence without interrupting the operation of either said cache memory unit or said SIU, said sequence control circuit including
• an address decision network including means for forming buffer pointers corresponding to read signals and write signals from said CPU, for receiving signals from said read and write buffers and for indicating to said CPU whether said read and write buffers can accept additional read and write signals from said CPU,
• a stack memory containing said buffer pointers which point to locations in said read and write buffers containing said read and write signals,
• a stack memory counter coupled to said address decision network to indicate at what location of said stack memory that said next buffer pointer is to be placed,
• a cache memory counter connected to said cache memory unit and responding to a signal from said cache memory unit to cause said stack memory to produce the buffer pointer that points to the position in said read buffer containing the read signal to be executed next by a said cache memory unit,
• a system interface unit counter connected to said SIU and responding to a signal from said SIU to cause said stack memory to produce the buffer pointer that points to the position in said read buffer containing the read signal to be executed next by said SIU, and
• a write counter connected to said cache memory counter and to said system interface unit counter and causing said stack memory to produce the buffer pointer that points to the location in said write buffer to said write signal to be executed next by said SIU or said cache memory unit.