G06F 12/0886
Variable-length word access
G06F12/0886 (Variable-length word access) appears on 406 US grants and 390 published applications in this corpus.
Search patents in G06F- Granted patents
- 406
- Published applications
- 390
- Assignees
- 137
- Inventors
- 850
- Latest grant
- 25 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1980 | 4 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 2 | 0 |
| 1992 | 3 | 0 |
| 1993 | 2 | 0 |
| 1994 | 4 | 0 |
| 1995 | 4 | 0 |
| 1996 | 4 | 0 |
| 1997 | 7 | 0 |
| 1998 | 8 | 0 |
| 1999 | 6 | 0 |
| 2000 | 5 | 0 |
| 2001 | 6 | 3 |
| 2002 | 10 | 3 |
| 2003 | 9 | 8 |
| 2004 | 6 | 13 |
| 2005 | 5 | 13 |
| 2006 | 6 | 9 |
| 2007 | 10 | 13 |
| 2008 | 15 | 12 |
| 2009 | 14 | 16 |
| 2010 | 7 | 11 |
| 2011 | 13 | 4 |
| 2012 | 11 | 15 |
| 2013 | 7 | 8 |
| 2014 | 11 | 12 |
| 2015 | 10 | 16 |
| 2016 | 22 | 18 |
| 2017 | 11 | 8 |
| 2018 | 15 | 14 |
| 2019 | 17 | 18 |
| 2020 | 9 | 24 |
| 2021 | 21 | 18 |
| 2022 | 23 | 30 |
| 2023 | 25 | 36 |
| 2024 | 28 | 30 |
| 2025 | 33 | 27 |
| 2026 | 12 | 11 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- System and method for cache management25 Aug 2026US 12,717,719 B2Samsung Electronics Co., Ltd.
- Index-based cache for key-value storage11 Aug 2026US 12,705,180 B2Twilio Inc.
- Methods, systems, and apparatuses for variable width unaligned fetch in a processor16 Jun 2026US 12,657,025 B2Intel Corporation
- Compute accelerated stacked memory26 May 2026US 12,639,003 B2Rambus Inc.
- Using a flag to indicate whether a mapping entry points to sequentially stored data12 May 2026US 12,625,805 B2
- Dynamic allocation of a last level cache (llc) to a feature in a head-mounted display (hmd)8 Oct 2026US 2026/0310607 A1QUALCOMM Incorporated
- Logical to Physical Translation Table Adapted to Facilitate Tracking of Data of a Storage Space of a Memory Sub-System Cached or Buffered in a Memory Space of the Memory Sub-System6 Aug 2026US 2026/0227907 A1Micron Technology, Inc.
- Processor and method providing an improved matrix storage9 Jul 2026US 2026/0195254 A1Intel Corporation
- Method for processing memory commands in computing system2 Jul 2026US 2026/0186971 A1Mediatek Inc.
- Prefetch kill and revival in an instruction cache2 Jul 2026US 2026/0186980 A1
Most cited
By later US patents
- Write-back cache protection398US 8,327,080 B1EMC Corporation · 2012
- Triple port cache memory143US 5,442,770 ANEC Electronics Corporation · 1995
- Partial cache line write transactions in a computing system with a write back cache123US 5,586,297 AHewlett-Packard Company · 1996
- Processor architecture for executing wide transform slice instructions117US 7,889,204 B2MicroUnity Systems Engineering, Inc. · 2011
- Cache memory and bus width control circuit for selectively coupling peripheral devices98US 5,280,598 AMitsubishi Denki Kabushiki Kaisha · 1994