Method for processing memory commands in computing system
AssigneeMediatek Inc.
InventorsYu-Wei Wang, Po-Han Wang, Teng-Feng Liao, Ke-Jen Lin
Life of this patent
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Abstract
A method for processing memory commands in a computing system comprises: transmitting, from a coherence hub to a downstream cache subsystem, a plurality of sub-commands, each of the sub-commands corresponding to a cache line size; receiving, at the downstream cache subsystem, at least one of the plurality of sub-commands; in response to receiving the at least one sub-command, determining, by the downstream cache subsystem, a full address range of the data block; and performing, by the downstream cache subsystem, an optimized memory operation directed to a downstream memory subsystem.
Claims20
A method for processing memory commands in a computing system, the method comprising:
- transmitting, from a coherence hub to a downstream cache subsystem, a plurality of sub-commands, each of the plurality of sub-commands corresponding to a cache line size;
- receiving, at the downstream cache subsystem, at least one of the plurality of sub-commands;
- in response to receiving the at least one sub-command, determining, by the downstream cache subsystem, a full address range of the data block;
- and
- performing, by the downstream cache subsystem, an optimized memory operation directed to a downstream memory subsystem.
A computing system, comprising:
- a coherence hub, configured to transmit a plurality of sub-commands, each of the plurality of sub-commands corresponding to a cache line size;
- and
- a downstream cache subsystem, configured to receive at least one of the plurality of sub-commands and in response to receiving the at least one sub-command, determine a full address range of the data block, and perform an optimized memory operation directed to a downstream memory subsystem, wherein the optimized memory operation corresponds to the full address range of the data block.
Dependencies are inferred from the claim text.