US 12,639,003 B2 · Compute accelerated stacked memory

Abstract

An integrated circuit that includes a set of one or more logic layers that are, when the integrated circuit is stacked in an assembly with the set of stacked memory devices, electrically coupled to a set of stacked memory devices. The set of one or more logic layers include a coupled chain of processing elements. The processing elements in the coupled chain may independently compute partial results as functions of data received, store partial results, and pass partial results directly to a next processing element in the coupled chain of processing elements. The processing elements in the chains may include interfaces that allow direct access to memory banks on one or more DRAMs in the stack. These interfaces may access DRAM memory banks via TSVs that are not used for global I/O. These interfaces allow the processing elements to have more direct access to the data in the DRAM.

Claims20

Dependent claims

An integrated circuit, comprising:

a set of one or more logic layers to interface to a set of stacked memory devices when the integrated circuit is stacked with the set of stacked memory devices;
and
the set of one or more logic layers comprising:
a serially coupled chain of processing elements, wherein:
respective outputs of processing elements are directly coupled to respective inputs of next processing elements in the serially coupled chain of processing elements;
and,
processing elements in the serially coupled chain are to independently of other processing elements in the serially coupled chain of processing elements compute partial results as functions of data received, store partial results, and pass partial results directly to a next processing element in the serially coupled chain of processing elements.

4 more elements

A system, comprising:

a set of stacked memory devices comprising memory cell circuitry;
a set of one or more processing devices electrically coupled to the set of stacked memory devices, the set of processing devices comprising:
a first set of at least two processing elements that are connected in a serial chain topology having respective outputs of processing elements in the first set directly coupled with respective inputs of next processing elements in the serial chain topology, where processing elements in the first set are to, independently of other of the first set of at least two processing elements, compute partial results using received data, to store partial results, and to directly pass partial results to a next processing element in the serial chain topology, wherein the first set includes a first input processing element to receive data from a first input interface to the first set and a first output processing element to pass results to a first output interface of the first set.

Dependencies are inferred from the claim text.

Compute accelerated stacked memory

Life of this patent

Compute accelerated stacked memory

Life of this patent

Abstract

Claims20