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US 2026/0064597 A1Published application
Split-entry dram cache
AssigneeRambus Inc.
InventorsMichael Raymond Miller, Wendy Elsasser, Brent Steven Haukness, Taeksang Song, Steven C. Woo
Life of this patent
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Abstract
A high-capacity cache memory is implemented by one or more DRAM dies in which individual cache entries are split across multiple DRAM storage banks such that each cache-line read or write is effected by a time-staggered set of read or write operations within respective storage banks spanned by the target cache entry.
Claims23
A dynamic random access memory (DRAM) cache comprising:
- a signaling interface to receive a cache access request;
- a DRAM array;
- and
- control circuitry to:
- access first and second storage banks within the DRAM array in response to the cache access request to render first and second memory pages into respective sets of sense amplifiers within the first and second storage banks;
- compare a search tag supplied with the cache access request with address tags stored within the first memory page to determine a cache hit/miss result;
- and
- access respective portions of a cache line entry within the first and second memory pages if the cache hit/miss result indicates a cache hit.
5 more elements
A method of operation within a dynamic random access memory cache (DRAM cache), the method comprising:
- accessing first and second storage banks within a DRAM array in response to a cache access request to render first and second memory pages into respective sets of sense amplifiers within the first and second storage banks;
- comparing a search tag supplied with the cache access request with address tags stored within the first memory page to determine a cache hit/miss result;
- and
- accessing respective portions of a cache line entry within the first and second memory pages if the cache hit/miss result indicates a cache hit.
1 more element
A dynamic random access memory (DRAM) cache comprising:
- a signaling interface to receive a cache access request;
- a DRAM array;
- means for accessing first and second storage banks within the DRAM array in response to the cache access request to render first and second memory pages into respective sets of sense amplifiers within the first and second storage banks;
- means for comparing a search tag supplied with the cache access request with address tags stored within the first memory page to determine a cache hit/miss result;
- and
- means for accessing respective portions of a cache line entry within the first and second memory pages if the cache hit/miss result indicates a cache hit.
3 more elements
Dependencies are inferred from the claim text.