Error correcting codes for multi-master memory controller

A system comprising:

• a memory controller;
• multiple memories coupled to the memory controller;
• and
• multiple controlling components coupled to the memory controller, wherein the memory controller is operable to:
• calculate an error correction code (ECC) syndrome of a first type for a segment of data;
• store the segment of data and the ECC syndrome of the first type in a first memory of the multiple memories;
• receive a request from a controlling component of the multiple controlling components directed to the segment of data, the controlling component operable to implement an ECC syndrome of a second type;
• transform the ECC syndrome of the first type for the segment of data to the ECC syndrome of the second type;
• detect a number of errors, if any, present in the segment of data;
• correct the error to generate a corrected segment of data based on the transform operation, when it is determined that one error is present in the segment of data;
• and
• send a response to the controlling component.

A system comprising:

• a memory controller;
• multiple memories, including a first memory and a second memory, coupled to the memory controller;
• and
• multiple controlling components coupled to the memory controller, wherein the memory controller is operable to:
• receive a transaction from a controlling component of the multiple controlling components, the transaction directed to the first memory and including an address;
• calculate an error correction code (ECC) for a segment of data in the second memory;
• determine that a non-correctable error is present in the segment of data in the second memory based on a comparison of the calculated ECC and a stored ECC for the segment of data;
• and
• terminate the transaction in response to determining that a non-correctable error is present in the segment of data in the second memory.