US 12,524,344 B1 · Cache writeback circuit

Abstract

A cache writeback circuit is disclosed for writing back, without invalidating, dirty cache lines. The cache writeback circuit is configured to enter an active state based on detecting a trigger condition indicative of cache misses to a memory cache circuit within a memory hierarchy of a computer memory subsystem causing cache line eviction activity. During the active state, the cache writeback circuit is configured to identify a set of dirty cache lines in the memory cache circuit, and write back, without invalidating, cache lines of the identified set of dirty cache lines from the memory cache circuit to a memory circuit within a lower level of the memory hierarchy, such as DRAM. The cache writeback circuit may further be configured to identify the dirty cache lines via a cache walk operation, which can be suspended, for example, when a higher-priority cache operation occurs.

Claims20

Dependent claims

An apparatus, comprising:

a computer system formed on one or more integrated circuits that includes:
a memory subsystem that includes a memory hierarchy with a memory cache circuit at a first level of the memory hierarchy and a volatile memory circuit at a second, lower level of the memory hierarchy;
a plurality of agent circuits configured to access the memory subsystem;
a cache writeback circuit configured to:
enter a cache writeback mode based on detection of read accesses from the plurality of agent circuits to the memory cache circuit that cause dirty data from the memory cache circuit to be written to the volatile memory circuit;
and
in the cache writeback mode, perform a cache walk of the memory cache circuit to identify dirty cache lines and write, without invalidating, the dirty cache lines from the memory cache circuit to the volatile memory circuit.

4 more elements

Dependencies are inferred from the claim text.

Cache writeback circuit

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Cache writeback circuit

Life of this patent

Abstract

Claims20