High speed burst read address generation with high speed transfer

A system comprising:

• a synchronous bus having address, command and data sections and operating according to a predetermined bus protocol;
• a unit coupled to said bus for generating commands for reading and writing memory, one of said commands specifying a burst operation in which any one of a plurality of predetermined sequences of addresses having a different initial address is supplied to said bus by said unit during a plurality of successive memory read cycles of operation;
• a memory tightly coupled to said unit through said synchronous bus, said memory comprising:
• a pair of dynamic random access memories (DRAMs) coupled to said bus, said DRAMs being organized for storing data words having even and odd addresses for enabling read out of a plurality of words during each memory read cycle of operation, each of said DRAMs having an identical width, the sum of the widths being no more than twice as wide as said data section of said bus and each DRAM memory including first and second data output circuits for receiving said plurality of data words read out during a predetermined number of successive memory read cycles of operation;
• an address register for storing said initial address of each of said plurality of predetermined address sequences;
• and
• address sequence control circuit means coupled to said DRAMs, said address sequence control circuit means including:
• first logic circuit means coupled to said address register, said first logic circuit means for selectively generating an output control signal for modifying the state of a first predetermined address bit signal of an initial address applied to said DRAMs during a predetermined one of said number of said successive memory read cycles of operation for generating all of said addresses for a first number of said plurality of predetermined address sequences;
• and,
• second logic circuit means coupled to said address section of said bus and to said first and second output data circuits of each of said DRAMs, said second logic circuit means including means for storing an indication of the state of a second predetermined address bit signal of said initial address of said one of said predetermined address sequences and means for selectively enabling different ones of said first and second data output output circuits of each of said DRAM memories as a function of said state of said indication of said state of second address bit signal stored by said means for storing during said predetermined number of said successive cycles of operation for transferring data read out to said first and second data output circuits during a plurality of bus cycles in an order corresponding to said addresses of a second number of said plurality of predetermined address sequences;
• and,
• increment/decrement circuit means connected to said address register, to said DRAMs, and to said address sequence control circuit means, said increment/decrement circuit means including a pair of tristate driver circuits and an inverter circuit, one of said pair of tristate driver circuits being connected to said address register for receiving said first predetermined address bit signal applied to said DRAMs, said inverter circuit being connected in common with said one tristate driver circuit for receiving said first predetermined address bit signal and to the other one of said pair of tristate driver circuits for applying an inverted first predetermined address bit signal, said other one of said pair of tristate driver circuits being connected to supply said inverted first predetermined address bit signal to said DRAMs, and said first logic circuit means being connected to said one and said other one of said pair of tristate driver circuits for supplying said output control signal and an inversion of said output control signal respectively for conditioning said tristate driver circuits during first and second intervals of each of said successive number of read cycles of operation for reading out a pair of words stored at even and odd addresses.