G06F 12/0817
Using directory methods
Official title: using directory methods
G06F12/0817 (Using directory methods) appears on 1,937 US grants and 1,788 published applications in this corpus.
Search patents in G06F- Granted patents
- 1,937
- Published applications
- 1,788
- Assignees
- 260
- Inventors
- 2,623
- Latest grant
- 1 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1979 | 1 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 2 | 0 |
| 1984 | 3 | 0 |
| 1985 | 2 | 0 |
| 1986 | 0 | 0 |
| 1987 | 3 | 0 |
| 1988 | 3 | 0 |
| 1989 | 0 | 0 |
| 1990 | 1 | 0 |
| 1991 | 5 | 0 |
| 1992 | 3 | 0 |
| 1993 | 13 | 0 |
| 1994 | 12 | 0 |
| 1995 | 2 | 0 |
| 1996 | 6 | 0 |
| 1997 | 15 | 0 |
| 1998 | 28 | 0 |
| 1999 | 33 | 0 |
| 2000 | 37 | 0 |
| 2001 | 24 | 6 |
| 2002 | 33 | 43 |
| 2003 | 48 | 49 |
| 2004 | 53 | 70 |
| 2005 | 57 | 52 |
| 2006 | 45 | 44 |
| 2007 | 31 | 49 |
| 2008 | 59 | 56 |
| 2009 | 42 | 51 |
| 2010 | 42 | 44 |
| 2011 | 43 | 36 |
| 2012 | 54 | 44 |
| 2013 | 49 | 58 |
| 2014 | 64 | 145 |
| 2015 | 103 | 88 |
| 2016 | 116 | 110 |
| 2017 | 95 | 97 |
| 2018 | 89 | 81 |
| 2019 | 111 | 105 |
| 2020 | 96 | 132 |
| 2021 | 101 | 72 |
| 2022 | 93 | 85 |
| 2023 | 100 | 78 |
| 2024 | 87 | 85 |
| 2025 | 91 | 80 |
| 2026 | 41 | 28 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Scope tree consistency protocol for cache coherence1 Sep 2026US 12,724,712 B2NVIDIA Corporation
- Concept for providing access to remote memory1 Sep 2026US 12,724,725 B2Intel Corporation
- Method of forming ferroelectric chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer25 Aug 2026US 12,717,479 B2Kepler Computing Inc.
- System and method for cache management25 Aug 2026US 12,717,719 B2Samsung Electronics Co., Ltd.
- Hardware pipeline for cache coherent interconnect including snoop filters18 Aug 2026US 12,711,070 B2Arteris, Inc.
- Methods and apparatus for eviction in dual datapath victim cache system1 Oct 2026US 2026/0300187 A1
- Cache coherence shared state suppression24 Sep 2026US 2026/0288640 A1
- Methods and apparatus to facilitate read-modify-write support in a victim cache17 Sep 2026US 2026/0277825 A1
- Merging data for write allocate10 Sep 2026US 2026/0267679 A1
- Ic apparatus with coherency domains10 Sep 2026US 2026/0267802 A1Arm Limited
Most cited
By later US patents
- Managing cache coherency in a data processing apparatus437US 7,937,535 B2Arm Limited · 2011
- Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system281US 5,655,100 ASun Microsystems, Inc. · 1997
- Multiple class memory systems214US 8,930,647 B1P4Tents1, LLC · 2015
- Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller201US 5,864,738 ACray Research, Inc. · 1999
- Cache coherency protocol for multi processor computer system200US 5,297,269 ADigital Equipment Corporation · 1994