Managing cache coherency in a data processing apparatus
AssigneeArm Limited
InventorsEmre Özer, Stuart David Biles, Simon Andrew Ford
Life of this patent
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AssigneeArm Limited
InventorsEmre Özer, Stuart David Biles, Simon Andrew Ford
Estimating the term…
Each of plural processing units has a cache, and each cache has indication circuitry containing segment filtering data. The indication circuitry responds to an address specified by an access request from an associated processing unit to reference the segment filtering data to indicate whether the data is either definitely not stored or is potentially stored in that segment. Cache coherency circuitry ensures that data accessed by each processing unit is up-to-date and has snoop indication circuitry whose content is derived from the already-provided segment filtering data. For certain access requests, the cache coherency circuitry initiates a coherency operation during which the snoop indication circuitry determines whether any of the caches requires a snoop operation. For each cache that does, the cache coherency circuitry issues a notification to that cache identifying the snoop operation to be performed.
A data processing apparatus, comprising:
A method of managing cache coherency in a data processing apparatus, the data processing apparatus comprising a plurality of processing units performing data processing operations requiring access to data in shared memory, each processing unit when access to data is required issuing an access request specifying an address in memory associated with that data, each processing unit having a cache associated therewith storing a subset of said data for access by that processing unit, said cache comprising a plurality of data arrays and a corresponding plurality of TAG arrays, each data array including a plurality of cache lines storing data values, and the corresponding TAG array having a plurality of TAG entries, where each TAG entry stores a TAG value that is associated with the data values in a corresponding cache line, the cache being arranged as a plurality of segments, where each segment comprises a plurality of said cache lines, each cache being responsive to at least a subset of the access requests issued by its associated processing unit to perform a lookup procedure involving access to at least one TAG array of the cache, each cache having indication circuitry associated therewith containing segment filtering data, the indication circuitry being separate from the TAG arrays of the cache and being responsive to an address portion of the address to reference the segment filtering data to provide, for each of at least a subset of the segments, an indication as to whether the data associated with that address is either definitely not stored in that segment or is potentially stored within that segment, the indications produced by the indication circuitry being used by the cache to affect the lookup procedure, the method comprising the steps of:
A data processing apparatus, comprising:
Dependencies are inferred from the claim text.