Hardware pipeline for cache coherent interconnect including snoop filters

A cache coherent interconnect for an electronic system, the cache coherent interconnect comprising:

• an interconnector;
• a system directory for maintaining cache coherence of the interconnector, the system directory including memory for storing a plurality of snoop filter way entries;
• and
• a plurality of pipelines for performing error correction on way entries from the memory, wherein each pipeline includes:
• a syndrome generator circuit configured to receive a way entry including raw data and raw check bits, and generate a syndrome from the raw data and the raw check bits;
• a buffer configured to store the raw data, the raw check bits and the syndrome prior to data correction;
• and
• a data correction circuit configured to receive the raw data, the raw check bits, and the syndrome from the buffer and correct the raw data with the syndrome.

An electronic system comprising:

• a plurality of caching agents;
• and
• a cache-coherent interconnect including a system directory and an interconnect,
• wherein the caching agents are configured to communicate with the system directory via the interconnect,
• wherein the system directory includes a plurality of snoop filters, each snoop filter including a plurality of way entries,
• wherein the system directory further includes a plurality of pipelines, each pipeline associated with one of the way entries and performing data correction on the associated way entry;
• and
• wherein each pipeline includes:
• a syndrome generator circuit configured to receive a corresponding way entry, and generate a syndrome from raw data and raw check bits in the corresponding way entry;
• a buffer configured to store the raw data, the raw check bits and the syndrome prior to data correction;
• and
• a data correction circuit configured to receive the raw data, the raw check bits, and the syndrome from the buffer and correct the raw data with the syndrome.