Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system

A computer system, comprising:

• a system controller;
• a multiplicity of sub-systems coupled to the system controller;
• a main memory coupled to said system controller;
• and
• a plurality of said sub-systems comprising data processors, a plurality of said data processors each having a respective cache memory that stores multiple blocks of data and a respective set of master ache tags (Etags), including one Etag for each data block stored by said cache memory;
• each of said data processors including an interface, coupled to said system controller, for sending memory transaction requests to said system controller;
• said interface for each of said data processors that has a cache memory including circuitry for receiving cache transaction requests from said system controller corresponding to memory transaction requests by other ones of said data processors;
• each memory transaction request having an associated address value;
• said system controller including:
• transaction activation logic for activating each said memory transaction request when it meets predefined activation criteria, and for blocking each said memory transaction request until said predefined activation criteria are met;
• an active transaction status table that stores active transaction status data representing memory transaction requests which have been activated by said transaction activation logic, said active transaction status data including data for each activated transaction presenting an address value associated with said transaction;
• and
• memory transaction request logic for processing each said memory transaction request after it has been activated by said transaction activation logic;
• a set of duplicate cache tags (Dtags) for each said cache memory, each Dtag corresponding to one of said Etags and storing a Dtag state value and the same address index as the corresponding Etag;
• said Dtag state value indicating whether the corresponding data block stored in a corresponding cache memory includes data modified by one of said data processors;
• said transaction activation logic including logic for comparing said each memory transaction request with said active transaction status data for all activated memory transaction requests so as to detect whether activation of said each memory transaction request would violate said predefined activation criteria with respect to any of said activated memory transaction requests;
• said memory transaction request logic including logic for accessing each said set of Dtags so as to determine whether it includes a Dtag corresponding to said memory transaction request, and logic for updating said Dtag state values, including logic for updating a specified Dtag state value from a valid to an invalid state value based on said memory transaction request;
• wherein said transaction activation logic blocks a transaction request by a second one of said data processors that violates said predefined activation criteria with respect to an activated memory transaction by a distinct, first one of said data processors.