G06F 12/0828
With concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
Official title: {with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions}
G06F12/0828 (With concurrent directory accessing, i.e. handling multiple concurrent coherency transactions) appears on 522 US grants and 533 published applications in this corpus.
Search patents in G06F- Granted patents
- 522
- Published applications
- 533
- Assignees
- 96
- Inventors
- 784
- Latest grant
- 1 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1979 | 1 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 1 | 0 |
| 1992 | 1 | 0 |
| 1993 | 0 | 0 |
| 1994 | 2 | 0 |
| 1995 | 2 | 0 |
| 1996 | 1 | 0 |
| 1997 | 5 | 0 |
| 1998 | 2 | 0 |
| 1999 | 7 | 0 |
| 2000 | 7 | 0 |
| 2001 | 5 | 1 |
| 2002 | 4 | 13 |
| 2003 | 13 | 3 |
| 2004 | 10 | 11 |
| 2005 | 9 | 12 |
| 2006 | 4 | 4 |
| 2007 | 4 | 5 |
| 2008 | 5 | 4 |
| 2009 | 9 | 9 |
| 2010 | 3 | 7 |
| 2011 | 5 | 3 |
| 2012 | 8 | 11 |
| 2013 | 9 | 16 |
| 2014 | 9 | 50 |
| 2015 | 34 | 40 |
| 2016 | 46 | 33 |
| 2017 | 31 | 38 |
| 2018 | 27 | 26 |
| 2019 | 49 | 36 |
| 2020 | 24 | 52 |
| 2021 | 37 | 21 |
| 2022 | 33 | 31 |
| 2023 | 34 | 27 |
| 2024 | 30 | 33 |
| 2025 | 32 | 31 |
| 2026 | 19 | 16 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Concept for providing access to remote memory1 Sep 2026US 12,724,725 B2Intel Corporation
- Method of forming ferroelectric chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer25 Aug 2026US 12,717,479 B2Kepler Computing Inc.
- Hardware pipeline for cache coherent interconnect including snoop filters18 Aug 2026US 12,711,070 B2Arteris, Inc.
- Global coherence operations4 Aug 2026US 12,699,589 B2Texas Instruments Incorporated
- Pseudo-random way selection7 Jul 2026US 12,675,312 B2Texas Instruments Incorporated
- Cache coherence shared state suppression24 Sep 2026US 2026/0288640 A1
- Merging data for write allocate10 Sep 2026US 2026/0267679 A1
- Ic apparatus with coherency domains10 Sep 2026US 2026/0267802 A1Arm Limited
- Pipeline arbitration3 Sep 2026US 2026/0259764 A1
- Hardware pipeline for cache coherent interconnect including snoop filters16 Jul 2026US 2026/0203223 A1Arteris, Inc.
Most cited
By later US patents
- Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system281US 5,655,100 ASun Microsystems, Inc. · 1997
- Cache coherency protocol for multi processor computer system200US 5,297,269 ADigital Equipment Corporation · 1994
- Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system110US 5,905,998 ASun Microsystems, Inc. · 1999
- Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed93US 5,603,005 AUnisys Corporation · 1997
- Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system92US 6,108,737 ACompaq Computer Corporation · 2000