US 6,108,737 A · Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system

Abstract

A mechanism reduces the latency of inter-reference ordering between sets of memory reference operations in a multiprocessor system having a shared memory. The mechanism comprises a commit-signal that is generated by control logic of the multiprocessor system in response to an issued memory reference operation. The commit-signal facilitates inter-reference ordering; moreover, the commit signal indicates the apparent completion of the memory reference operation, rather than actual completion of the operation. The apparent completion of an operation occurs substantially sooner than the actual completion of an operation, thereby improving performance of the multiprocessor system.

Claims21

Dependent claims

Apparatus for reducing latency of inter-reference ordering between memory reference operations of a shared memory multiprocessor system having a consistency model, the system having a plurality of processors, each processor capable of issuing a memory reference operation to the system, the apparatus comprising:

a commit-signal structure generated by control logic of the multiprocessor system in response to each issued memory reference operation, the commit-signal generated substantially sooner than completion of the memory reference operation, the commit-signal indicating apparent completion of the memory reference operation rather than actual completion of the operation;
wherein each processor employs the commit signal to impose inter-reference ordering.

Apparatus for reducing the latency of inter-reference ordering between memory reference operations issued by a processor to a symmetric multiprocessing (SMP) node having a shared memory that is distributed among a plurality of processors, each processor having a private cache and a programming interface to the distributed shared memory, the apparatus comprising:

a local switch of the SMP node, the local switch interconnecting the processors and shared memory;
an ordering point coupled to the local switch and configured to totally order the memory reference operations issued to the node;
and
a commit-signal structure generated by the ordering point in response to each memory reference operation issued to the node, the commit-signal indicating the apparent completion of the memory reference operation to the processor issuing the operation.

1 more element

Apparatus for reducing the latency of inter-reference ordering between memory reference operations issued by a processor to a symmetric multiprocessing (SMP) system comprising a plurality of SMP nodes, each node having a shared memory that is distributed among a plurality of processors, each processor having a private cache and a programming interface to the distributed shared memory, the apparatus comprising:

a hierarchical switch of the SMP system, the hierarchical switch interconnecting the plurality of SMP nodes;
an ordering point of the hierarchical switch configured to atomically multicast and totally order the memory reference operations issued to the system;
and
a commit-signal structure generated by the ordering point in response to each memory reference operation issued to the system, the commit-signal comprising one of a plurality of commit-signal types, each type of commit-signal indicating the apparent completion of the memory reference operation to the processor issuing the operation.

1 more element

Dependencies are inferred from the claim text.

Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system

Life of this patent

Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system

Life of this patent

Abstract

Claims21