G06F 12/082
Associative directories
Official title: {Associative directories (G06F12/0822 takes precedence)}
G06F12/082 (Associative directories) appears on 257 US grants and 270 published applications in this corpus.
Search patents in G06F- Granted patents
- 257
- Published applications
- 270
- Assignees
- 70
- Inventors
- 412
- Latest grant
- 16 Jun 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1993 | 1 | 0 |
| 1994 | 1 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 1 | 0 |
| 1998 | 4 | 0 |
| 1999 | 2 | 0 |
| 2000 | 5 | 0 |
| 2001 | 4 | 1 |
| 2002 | 3 | 7 |
| 2003 | 8 | 14 |
| 2004 | 4 | 10 |
| 2005 | 12 | 7 |
| 2006 | 10 | 6 |
| 2007 | 3 | 11 |
| 2008 | 14 | 8 |
| 2009 | 5 | 8 |
| 2010 | 6 | 7 |
| 2011 | 7 | 5 |
| 2012 | 5 | 10 |
| 2013 | 8 | 4 |
| 2014 | 6 | 22 |
| 2015 | 12 | 9 |
| 2016 | 15 | 12 |
| 2017 | 10 | 2 |
| 2018 | 3 | 9 |
| 2019 | 7 | 7 |
| 2020 | 11 | 34 |
| 2021 | 8 | 7 |
| 2022 | 18 | 13 |
| 2023 | 21 | 14 |
| 2024 | 20 | 20 |
| 2025 | 18 | 18 |
| 2026 | 5 | 5 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Methods and apparatus for eviction in dual datapath victim cache system16 Jun 2026US 12,657,134 B2Texas Instruments Incorporated
- Methods and apparatus for inflight data forwarding and invalidation of pending writes in store queue16 Jun 2026US 12,657,135 B2Texas Instruments Incorporated
- Point-of-coherence exclusive monitor for a cache coherent interconnect for a multi-core electronic system2 Jun 2026US 12,645,595 B1Arteris, Inc.
- Methods and apparatus to facilitate read-modify-write support in a victim cache12 May 2026US 12,625,822 B2Texas Instruments Incorporated
- Methods and apparatus to reduce read-modify-write cycles for non-aligned writes3 Feb 2026US 12,541,468 B2Texas Instruments Incorporated
- Methods and apparatus for eviction in dual datapath victim cache system1 Oct 2026US 2026/0300187 A1
- Methods and apparatus to facilitate read-modify-write support in a victim cache17 Sep 2026US 2026/0277825 A1
- Method for processing memory commands in computing system2 Jul 2026US 2026/0186971 A1Mediatek Inc.
- Systems and methods for region-based probe filter shootdown26 Mar 2026US 2026/0086950 A1Advanced Micro Devices, Inc.
- Victim cache that supports draining write-miss entries5 Feb 2026US 2026/0037451 A1
Most cited
By later US patents
- Optimum write-back strategy for directory-based cache coherence protocols104US 5,313,609 AInternational Business Machines Corporation · 1994
- Method and apparatus for maintaining cache coherency in a computer system having multiple processor buses99US 6,304,945 B1Compaq Computer Corporation · 2001
- Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data94US 5,265,232 AInternational Business Machines Corporation · 1993
- Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls80US 6,457,100 B1International Business Machines Corporation · 2002
- Hybrid memory access protocol in a distributed shared memory computer system72US 6,496,854 B1Sun Microsystems, Inc. · 2002