Point-of-coherence exclusive monitor for a cache coherent interconnect for a multi-core electronic system
AssigneeArteris, Inc.
InventorBoon Chuan
Life of this patent
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Abstract
An electronic system includes a plurality of logical processors, an interconnect, shared memory accessible by the logical processors via the interconnect, and a system directory. The system directory includes one or more tagged monitors at a first tier and a basic monitor at a second tier. The tagged monitors are configured to maintain exclusive cache coherence over a first set of addresses in the shared memory. The basic monitor is configured to maintain exclusive cache coherence over addresses in the shared memory that are not monitored by the tagged monitors.
Claims20
An electronic system comprising:
- a plurality of logical processors;
- an interconnect;
- shared memory accessible by the logical processors (LPs) via the interconnect;
- and
- a system directory including one or more tagged monitors at a first tier and a basic monitor at a second tier, the tagged monitors configured to maintain exclusive cache coherence over a first set of addresses in the shared memory, the basic monitor configured to maintain exclusive cache coherence over addresses in the shared memory that are not monitored by the tagged monitors.
A cache coherent network on chip (NoC) comprising:
- a plurality of initiator network interface units;
- a shared memory network interface unit;
- a transport interconnect configured to transport packets between the network interface units;
- and
- a system directory including one or more tagged monitors at a first tier and a basic monitor at a second tier, the tagged monitors configured to maintain exclusive cache coherence over a set of semaphore addresses in the shared memory, the basic monitor configured to maintain exclusive cache coherence over semaphore addresses in the shared memory that are not monitored by the tagged monitors.
A directory-based method for an electronic system including a plurality of initiators, shared memory and an interconnect coupled to the initiators and the shared memory, the method comprising:
- performing tagged monitoring at a first tier to maintain exclusive cache coherence over a set of cache line addresses in the shared memory;
- and
- concurrently performing basic monitoring at a second tier to maintain exclusive cache coherence over cache line addresses in the shared memory that are not monitored by the tagged monitors.
Dependencies are inferred from the claim text.