Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls

A scaleable computer system constructed of replicatable semiconductor chips in one or more nodes, in which the size of any node and/or the number of nodes in the system can be easily varied to change the size and performance of the computer system, each node in the computer system comprising:

• a plurality of processor semiconductor chips (processor chips) within each node, each processor chip containing at least one central processor having a private cache (L1 cache) and a memory controller in each processor chip, the processor chips each having the same manufacturing specification to support easy replicatability,
• a plurality of RAM (random access memory) semiconductor chips (RAMs) forming a shared memory in the computer system accessible to all central processors on all processor chips in the computer system, the shared memory being comprised of the totality of RAMs in the computer system, the shared memory being separated into a plurality of subsets of the RAMs (RAM sections), each RAM section being connected to a memory controller on a different processor chip in the computer system,
• a plurality of local memory buses, each memory bus being locally connected between a respective RAM section and a respective memory controller on a respective processor chip for direct access between a locally connected RAM section for each processor on the respective processor chip,
• a nodal cache in each node, each nodal cache being connected to each processor chip in the same node for storing data accessed in the shared memory by any central processor in the same node,
• a nodal directory in each node connected to the nodal cache in the same node, each nodal directory connected to each processor chip in the same node, and
• intra-nodal busing in each node for connecting each processor chip to the nodal cache and nodal directory in the same node to enable any processor in the node to access data on any RAM section of the shared memory of the node when any processor is accessing a RAM section not directly connected to the processor chip containing the processor, and
• one or more replicatable nodal cache semiconductor chips (nodal cache chips) form the nodal cache of each node used for storing data accessed by the central processors in the node or stored in the RAM, and each replicatable nodal cache semiconductor chip of the nodal cache is connected to the nodal directory of the same node, the nodal directory locating processor-requested data in the nodal cache, and
• an intra-nodal electronic switch connects the nodal directory and each nodal cache chip to each processor chip in the same node and enables data being stored in the RAM section connected to each processor chip being quickly accessible to and usable by any processor on the processor chip overlapping with an access to the nodal cache or nodal directory for determining if a changed copy of the data exists anywhere in the system, and wherein controls in each processor chip for requesting data from the connected nodal cache with a processor-requested address of the data to the connected nodal directory control fetching of the data from the connected nodal cache when the data is not available as short-path data in the RAMs connected to the requesting processor chip, and nodal controls of the nodal directory fetch data from the connected nodal cache when the data is currently contained in the connected nodal cache, and nodal miss controls of the nodal directory respond when the data is not contained in the connected nodal cache with a nodal request for the data to a processor chip connected to a RAM section having the processor requested address, and the nodal-requested processor chip sends a copy of data at the requested address to the nodal cache, which data is then sent by the nodal cache to the processor providing the processor requested address which had missed in the nodal cache and
• further comprising
• a plurality of identical nodal cache chips comprising the nodal cache, in which each nodal cache chip stores a fraction of each line of data (each data line) stored in the nodal cache, each data line being a unit of data determined by a single access in the shared memory.