Method and apparatus for maintaining cache coherency in a computer system having multiple processor buses

A memory system for receiving memory requests from a plurality of processor buses, comprising:

• an address bus adapted to receive a memory request from one of the processor buses;
• a main memory adapted to store lines of data;
• a distributed coherency filter coupled to the address bus, the distributed coherency filter being adapted to store coherency information related to the lines of data associated with each of the processor buses and to access the coherency information based on the memory request;
• and
• a memory device coupled to the distributed coherency filter, the memory device being divided into blocks, each block being adapted to store at least a portion of the cache lines associated with a particular one of the processor buses.

A method for maintaining cache coherency among processors coupled to a plurality of processor buses, comprising:

• storing lines of data in a main memory;
• receiving a memory request for a particular line of data in the main mem ory from one of the processor buses;
• storing coherency information related to the lines of data associated with each of the processor buses in a memory device having a plurality of blocks, each block being adapted to store at least a portion of the cache lines associated with a particular one of the processor buses;
• and
• accessing the coherency information based on the memory request.

A memory system for maintaining cache coherency among processors coupled to a plurality of processor buses, comprising:

• means for storing lines of data;
• means for receiving a memory request for a particular line of the data from one of the processor buses;
• means for storing coherency information related to the lines of data associated with each of the processor buses in a memory device having a plurality of blocks, each block being adapted to store at least a portion of the cache lines associated with a particular one of the processor buses;
• and
• means for accessing the coherency information based on the memory request.

A computer system, comprising:

• a plurality of processor buses;
• a plurality of processors coupled to the processor buses, at least a portion of the processors having associated cache memories arranged in cache lines;
• and
• a memory bank coupled to the processor buses, the memory bank comprising:
• a main memory adapted to store data corresponding to at least a portion of the cache lines;
• and
• a distributed coherency filter adapted to store coherency information related to the cache lines associated with each of the processor buses;
• an address bus coupled to the distributed coherency filter, the address bus being adapted to receive a memory request including a request address from one of the processor buses, and the distributed coherency filter being adapted to retrieve the coherency information based on at least a portion of the request address;
• and
• a memory address controller coupled to the address bus in parallel with the distributed coherency filter for receiving the request address and coupled to the main memory for accessing the data therein based on the request address.

A memory system for receiving memory requests from a plurality of processor buses, comprising:

• an address bus adapted to receive a memory request from one of the processor buses;
• a main memory adapted to store lines of data;
• a distributed coherency filter coupled to the address bus, the distributed coherency filter being adapted to store coherency information related to the lines of data associated with each of the processor buses, and to access the coherency information based on the memory request;
• and
• a memory address controller coupled to the address bus in parallel with the distributed coherency filter for receiving the request address and coupled to the main memory for accessing the data therein based on the request address.

A method for maintaining cache coherency among processors coupled to a plurality of processor buses, comprising:

• storing lines of data in a main memory;
• receiving a memory request for a particular line of data in the main memory from one of the processor buses;
• storing coherency information related to the lines of data associated with each of the processor buses;
• accessing the coherency information based on the memory request;
• and
• accessing the main memory in parallel with accessing the coherency information.

A memory system for maintaining cache coherency among processors coupled to a plurality of processor buses, comprising:

• means for storing lines of data in a main memory;
• means for receiving a memory request for a particular line of data in the main memory from one of the processor buses;
• means for storing coherency information related to the lines of data associated with each of the processor buses;
• means for accessing the coherency information based on the memory request;
• and
• means for accessing the main memory in parallel with accessing the coherency information.