Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data

Coherence means for a data processing system, comprising:

• a plurality of CPU caches, and a backing memory containing data units that can be copied into the CPU caches;
• each CPU cache having a CPU directory means having plural entries, each entry having a valid field for indicating if the entry has an associated data unit in a corresponding CPU cache slot, and having an exclusive field for indicating either exclusive (EX) ownership with write capability or public (RO) ownership with only read capability of the associated data unit;
• a coherence directory in the system having a plurality of entries, each coherence directory entry having a valid field, an address field, and a CPU identifier field, the address field containing an address representation of an associated data unit in the backing memory, and the CPU identifier field identifying a CPU having ownership of the data unit when the valid field indicates the entry is valid;
• and
• means for providing a cross-invalidation (XI) signal to a CPU identified in an accessed entry in the coherence directory as having exclusive ownership of the associated data unit when a request is made to change the ownership of the associated data unit.

Coherence means for a data processing system having a plurality of CPUs with private L1 caches, and the system having a shared storage containing data units accessible to the L1 caches, comprising:

• shared directory means having a plurality of entries connected to the L1 caches for controlling data coherence in the system, each entry including:
• a valid field, an EX field, a CPU identifier (CPID) field, and an address representation for representing the location of an associated data unit in the shared storage, the valid field being set to a valid or invalid state for indicating if the entry represents an associated data unit in the shared storage, the EX field being set to indicate exclusive ownership state (EX) by the CPU identified in the CPID field if the CPU is to be enabled to write and read the associated data unit, or the EX field being reset to indicate a public ownership state (RO) if one or more of plural CPUs in the system are enabled to read but not write into the associated data unit;
• and
• means for providing an invalidation request signal to the CPU identified in the CPID field to terminate the current CPU ownership of the associated data unit when another CPU requests exclusive ownership of the data unit.

Coherence means for a data processing system, comprising:

• a plurality of CPUs, each CPU having at least one private cache with a related directory having a plurality of entries, each CPU requested address simultaneously addressing an entry in a CPU directory and an associated data unit slot in the related CPU cache, means in each entry for indicating exclusive ownership of a data unit in the associated slot for writing into the data unit;
• a coherence directory having a plurality of entries for receiving requests from a plurality of CPUs, each entry having an address representation for locating an associated data unit in a backing memory, each entry also containing means for identifying one of the CPUs in the system as having exclusive authority to write into the associated data unit;
• means for providing a specific cross-invalidation (XI) signal only to a CPU identified in an accessed entry in the coherence directory for terminating the CPU's exclusive ownership of the associated data unit when an access request is made to the coherence directory to change the ownership of the data unit;
• and
• means with each CPU for signalling an XI response for indicating the CPU is giving up its exclusive ownership of the XI request's data unit.

Coherence means for a data processing system having a plurality of CPUs with private L1 caches, and the system having a shared storage containing data units accessible to the L1 caches, comprising:

• providing a single shared directory means having a plurality of entries connected to the L1 caches for controlling data coherence in the system, each entry including:
• a valid field, an EX field, a CPU identifier (CPID) field, and an address representation for representing the location of an associated data unit in the shared storage, the valid field being set to a valid or invalid state for indicating if the entry represents an associated data unit in the shared storage, the EX field being set to indicate exclusive ownership state (EX) by the CPU identified in the CPID field if the CPU is to be enabled to write and read the associated data unit, or the EX field being reset to indicate a public ownership state (RO) if one or more of plural CPUs in the system are enabled to read but not write into the associated data unit;
• and
• signalling an invalidation request to the CPU identified in the CPID field to terminate the current CPU ownership of the associated data unit when another CPU requests exclusive ownership of the data unit.

A coherence method for a data processing system to support parallelism of processor requests to a backing memory, comprising the steps of:

• structuring the backing memory from a plurality of backing memory sections for containing backing data for a plurality of private processor caches in the system, each backing memory section having an assigned address range,
• providing a plurality of coherence (XI) directory sections respectively associated with the backing memory sections, and entries in each XI directory section being restricted to supporting processor addresses in the assigned address range of an associated backing memory section,
• registering a requested address from any of plural processors in the system in the XI directory section having the assigned address range containing the requested address, each XI directory section being shared by the processors in the system for requested addresses in the assigned memory range of the associated backing memory section, and
• performing coherence control in parallel in the XI directory sections for requested addresses concurrently sent by plural processors to different XI directory sections in response to misses by processor requested addresses in the private caches of the processors.