Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller

A massively parallel processing system, comprising:

• an interconnect network;
• a plurality of processing nodes, wherein each processing node includes:
• a processor;
• local memory;
• and
• a router circuit connected to the interconnect network, the processor and the local memory, wherein the router circuit includes first and second data paths, wherein the router circuit transfers data between the processor and the interconnect network and between the local memory and the interconnect network over said first data path;
• a peripheral device;
• and
• a plurality of I/O controllers, including a first I/O controller, wherein each I/O controller is connected to the second data path of a plurality of the router circuits and wherein each router circuit further includes I/O routing means for transferring data between the I/O controller to which the router circuit is connected and local memory of any of the plurality of processing nodes
• a plurality of I/O controllers, including a first I/O controller, wherein each I/O controller is connected to a plurality of router circuits, wherein each router circuit further includes means for transferring data between the I/O controller to which the router circuit is connected and local memory of any of the plurality of processing nodes and wherein the first I/O controller includes peripheral interface means for transferring data from the peripheral device to the local memory on one of the plurality of processing nodes.

A method of transferring data between a peripheral device and a massively parallel processing system having an interconnect network and a plurality of processing nodes, wherein each processing node includes a processor, local memory and a router circuit connected to the interconnect network, the processor and the local memory, wherein the router circuit includes a first and a second data path, wherein the router circuit transfers data between the processor and the interconnect network and between the local memory and the interconnect network over said first data path:

• providing an I/O controller;
• connecting the I/O controller to the second data path of a plurality of router circuits;
• reading data from the peripheral device;
• transferring the data read from the peripheral device from the I/O controller to one of the plurality of router circuits connected to the I/O controller;
• and
• transferring the data read from the peripheral device from the one of the plurality of router circuits connected to the I/O controller across the interconnect network to the local memory of one of the plurality of processing nodes.