Translucent, Inc.
Cleveland, OH, US· latest recorded location
Translucent, Inc. is named on 65 US grants and 53 published applications in this corpus. Its most frequent classification is H10P (Generic processes or apparatus for the manufacture or treatment of devices covered).
- Granted patents
- 65
- Published applications
- 53
- Inventors
- 16
- Granted in 2026 so far
- 0
- Most recent grant
- 23 Sep 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2004 | 0 | 1 |
| 2005 | 0 | 2 |
| 2006 | 3 | 4 |
| 2007 | 2 | 3 |
| 2008 | 4 | 3 |
| 2009 | 6 | 2 |
| 2010 | 6 | 7 |
| 2011 | 6 | 4 |
| 2012 | 2 | 9 |
| 2013 | 6 | 4 |
| 2014 | 17 | 7 |
| 2015 | 4 | 4 |
| 2016 | 6 | 2 |
| 2017 | 1 | 1 |
| 2018 | 1 | 0 |
| 2019 | 0 | 0 |
| 2020 | 0 | 0 |
| 2021 | 0 | 0 |
| 2022 | 0 | 0 |
| 2023 | 0 | 0 |
| 2024 | 0 | 0 |
| 2025 | 1 | 0 |
By publication year.
Technology areas
Share of 118 documents
- H10PGeneric processes or apparatus for the manufacture or treatment of devices covered69
- H10DInorganic electric semiconductor devices60
- H10HInorganic light-emitting semiconductor devices having potential barriers25
- H10FSolar cells and light sensors24
- Y02EClean energy generation and storage24
- H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by18
- B82YSpecific uses or applications of nanostructures16
- H01SDevices using the process of light amplification by stimulated emission of radiation14
- C30BSingle-crystal growth12
- G02BOptical elements, systems or apparatus11
Recent patents
- Signage plate23 Sep 2025US D1,094,547 S1Design
- III-N semiconductor layer on Si substrate13 Mar 2018US 9,917,193 B2
- Stress mitigating amorphous SiO2 interlayer21 Nov 2017US 9,824,886 B2
- Nucleation of III-N on REO templates15 Nov 2016US 9,496,132 B2
- Method of growing III-N semiconductor layer on Si substrate4 Oct 2016US 9,460,917 B2
- Iii-n semiconductor layer on si substrate23 Feb 2017US 2017/0054025 A1
- Stress mitigating amorphous sio2 interlayer18 Aug 2016US 2016/0240375 A1
- Strain compensated reo buffer for iii-n on silicon12 May 2016US 2016/0133708 A1
- Iii-n semiconductor layer on si substrate13 Aug 2015US 2015/0228484 A1
- Ren semiconductor layer epitaxially grown on realn/reo buffer on si substrate23 Jul 2015US 2015/0203990 A1
Most cited
By later US patents
- Semiconductor-on-insulator silicon wafer274US 7,217,636 B12007
- Thermoelectric and pyroelectric energy conversion devices30US 7,807,917 B22010
- Semiconductor structures with rare-earths24US 8,106,381 B22012
- Method of fabricating silicon-on-insulator semiconductor substrate using rare earth oxide or rare earth nitride19US 7,037,806 B12006
- Semiconductor-on-insulator silicon wafer and method of formation16US 7,018,484 B12006