H03L 7/0893
The up-down pulses controlling at least two source current generators or at
Official title: {the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop}
H03L7/0893 (The up-down pulses controlling at least two source current generators or at) appears on 377 US grants and 302 published applications in this corpus.
Search patents in H03L- Granted patents
- 377
- Published applications
- 302
- Assignees
- 171
- Inventors
- 608
- Latest grant
- 4 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1979 | 1 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 1 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 3 | 0 |
| 1989 | 1 | 0 |
| 1990 | 0 | 0 |
| 1991 | 2 | 0 |
| 1992 | 3 | 0 |
| 1993 | 1 | 0 |
| 1994 | 4 | 0 |
| 1995 | 7 | 0 |
| 1996 | 6 | 0 |
| 1997 | 3 | 0 |
| 1998 | 7 | 0 |
| 1999 | 8 | 0 |
| 2000 | 8 | 0 |
| 2001 | 13 | 7 |
| 2002 | 10 | 11 |
| 2003 | 17 | 13 |
| 2004 | 17 | 24 |
| 2005 | 16 | 29 |
| 2006 | 26 | 24 |
| 2007 | 30 | 27 |
| 2008 | 22 | 17 |
| 2009 | 14 | 18 |
| 2010 | 13 | 16 |
| 2011 | 9 | 8 |
| 2012 | 21 | 10 |
| 2013 | 17 | 10 |
| 2014 | 10 | 13 |
| 2015 | 9 | 1 |
| 2016 | 8 | 9 |
| 2017 | 7 | 2 |
| 2018 | 4 | 5 |
| 2019 | 9 | 10 |
| 2020 | 13 | 8 |
| 2021 | 7 | 10 |
| 2022 | 4 | 6 |
| 2023 | 9 | 9 |
| 2024 | 7 | 4 |
| 2025 | 6 | 8 |
| 2026 | 2 | 3 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
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- Buffer circuit, and semiconductor apparatus capable of adjusting a clock receiver and/or changing a clock path according to frequency information2 Jun 2026US 12,645,248 B2SK hynix Inc.
- Systems and methods for phase locked loop realignment with skew cancellation22 Jul 2025US 12,368,444 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Triple-path clock and data recovery circuit, oscillator circuit and method for clock and data recovery24 Jun 2025US 12,341,522 B2M31 Technology Corporation
- Dual loop charge pump for enhanced reliability and power consumption20 May 2025US 12,308,847 B2International Business Machines Corporation
- Buffer circuit, and semiconductor apparatus capable of adjusting a clock receiver and/or changing a clock path according to frequency information10 Sep 2026US 2026/0267370 A1SK hynix Inc.
- Dual-path phase-locked loop21 May 2026US 2026/0142664 A1NXP USA, Inc.
- An apparatus26 Mar 2026US 2026/0088823 A1NXP B. V.
- Phase-locked loop circuit25 Dec 2025US 2025/0392317 A1Samsung Electronics Co., Ltd.
- Phase-locked loop4 Dec 2025US 2025/0373252 A1ams-OSRAM AG
Most cited
By later US patents
- Phase locked loop circuit having regulator98US 7,616,075 B2Kabushiki Kaisha Toshiba · 2009
- Digital phase detector and charge pump system reset and balanced current source matching96US 6,140,853 ACypress Semiconductor Corporation · 2000
- Delta-sigma based dual-port modulation scheme and calibration techniques for similar modulation schemes90US 6,515,553 B1Conexant Systems, Inc. · 2003
- Phase-locked loop circuit and delay-locked loop circuit89US 6,954,511 B2Sony Corporation · 2005
- Methods and apparatus for generating multiple clocks using feedback interpolation86US 7,323,916 B1NetLogic Microsystems, Inc. · 2008