Methods and apparatus for generating multiple clocks using feedback interpolation

A frequency synthesis circuit comprising:

• clock synthesis circuit for receiving a reference clock and for generating a first clock signal at a first frequency;
• phase locked loop circuit for receiving said reference clock signal and a feedback clock signal and for generating a second clock signal comprising a second frequency, wherein said first and second frequencies are different frequencies;
• interpolator circuit, coupled in a feedback path to said phase locked loop circuit, for receiving said second clock signal and for generating said feedback clock signal by introducing a time delay in said second clock signal that varies over time so as to change said second frequency of said second clock signal;
• and
• interpolator control circuit, coupled to said interpolator circuit, for controlling said variable time delay introduced by said interpolator, said interpolator control circuit comprising a digital for generating an interpolator control word that controls said variable time delay in said interpolator, and wherein said interpolator control word comprises a clock offset word to define an offset between said first frequency and said second frequency.

A method for generating two clock signals from a single reference, said method comprising:

• generating a first clock signal at a first frequency from a reference clock;
• receiving said reference clock and a feedback clock as inputs to a phase locked loop circuit;
• generating a second clock signal, comprising a second frequency, as an output of said phase locked loop circuit, wherein said first and second frequencies are different frequencies;
• generating said feedback clock by introducing a time delay in said second clock signal clock that varies over time so as to change said second frequency of said second clock signal;
• and
• generating an interpolator control word, comprising a clock offset word to define an offset between said first frequency and said second frequency word, to control said variable time delay.

A method for generating two clock signals from a single reference, said method comprising:

• generating a first clock at a first frequency from a reference clock;
• receiving said first clock signal and a feedback as inputs to a phase locked loop circuit;
• generating a second clock signal, comprising a second frequency, as an output of said phase locked loop circuit, wherein said first and second frequencies are different frequencies;
• generating said feedback clock by introducing a time delay in said second clock signal clock that varies over time so as to change said second frequency of said second clock signal;
• and
• generating as interpolator control word, comprising a clock offset word to define an offset between said first frequency and said frequency word, to control said variable delay.