US 6,954,511 B2 · Phase-locked loop circuit and delay-locked loop circuit

Abstract

A PLL circuit and a DLL circuit able to stabilize a control voltage within a short time after a phase pull-in operation in each cycle of a reference clock. In a phase comparator, the size of a leading phase or a delayed phase of a feedback signal is detected with respect to a reference clock signa, and pulse signals having pulse widths corresponding to the size are output. A current corresponding to the signals is output from a charge pump circuit to a lag-lead filter, and a control voltage obtained by removing noise of the above output is output from a low-pass filter to a voltage-controlled oscillator. Furthermore, through capacitors, pulse signals are superposed on the control voltage, and a sharp waveform is obtained by correcting blunting of the waveform by the low-pass filter. Due to this, the control voltage is stabilized within a short time after a phase pull-in operation in each cycle of the reference clock signal.

Claims46

Dependent claims

A phase-locked loop circuit comprising:

a phase comparison means for detecting a size of a leading phase or a delayed phase of a feedback signal with respect to a reference signal and outputting a leading phase signal having a pulse width corresponding to the size of the leading phase or a delayed phase signal having a pulse width corresponding to the size of the delayed phase;
a smoothing means for smoothing the leading phase signal or the delayed phase signal output from the phase comparison means and outputting the result as a control signal;
a superposing means for superposing the leading phase signal or the delayed phase signal output from the phase comparison means on the control signal;
and
an oscillation circuit for receiving the control signal superposed with other signals by the superposing means and outputting the feedback signal of a frequency corresponding to the control signal to the phase comparison means.

2 more elements

A phase-locked loop circuit comprising a phase comparison means for detecting a size of a leading phase or a delayed phase of a feedback signal with respect to a reference signal and outputting a leading phase signal having a pulse width corresponding to the size of the leading phase or a delayed phase signal having a pulse width corresponding to the size of the delayed phase,

a smoothing means for smoothing the leading phase signal or the delayed phase signal output from the phase comparison means and outputting the result as a control signal,
a bias signal generating means for outputting a first bias signal and a second bias signal corresponding to the control signal,
a noise filter for removing noise components included in the first bias signal and the second signal,
a first superposing means for superposing the leading phase signal or the delayed phase signal output from the phase comparison means on the first bias signal,
a second superposing means for superposing the leading phase signal or the delayed phase signal output from the phase comparison means on the second bias signal, and
an oscillation circuit which includes a plurality of delay stages for exchanging and outputting a first current variable according to the first bias signal superposed with other signals by the first superposing means and a second current variable according to the second bias signal superposed with other signals by the second superposing means according to levels of input signals, feeds back an output signal of a last delay stage to an input of a first delay stage, and outputs an output signal of one of the delay stages as the feedback signal to the phase comparison means.

3 more elements

A delay-locked loop circuit comprising

a phase comparison means for detecting a size of a leading phase or a delayed phase of a feedback signal with respect to a reference signal and outputting a leading phase signal having a pulse width corresponding to the size of the leading phase or a delayed phase signal having a pulse width corresponding to the size of the delayed phase,
a smoothing means for smoothing the leading phase signal or the delayed phase signal output from the phase comparison means and outputting the result as a control signal,
a superposing means for superposing the leading phase signal or the delayed phase signal output from the phase comparison means on the control signal, and
a delay circuit for receiving the control signal superposed with other signals by the superposing means and the reference signal and outputting to the phase comparison means the feedback signal having a delay corresponding to the control signal relative to the reference signal.

1 more element

A delay-locked loop circuit comprising

a phase comparison means for detecting a size of a leading phase or a delayed phase of a feedback signal with respect to a reference signal and outputting a leading phase signal having a pulse width corresponding to the size of the leading phase or a delayed phase signal having a pulse width corresponding to the size of the delayed phase,
a smoothing means for smoothing the leading phase signal or the delayed phase signal output from the phase comparison means and outputting the result as a control signal,
a bias signal generating means for outputting a first bias signal and a second bias signal corresponding to the control signal,
a noise filter for removing noise components included in the first bias signal and the second signal,
a first superposing means for superposing the leading phase signal or the delayed phase signal output from the phase comparison means on the first bias signal,
a second superposing means for superposing the leading phase signal or the delayed phase signal output from the phase comparison means on the second bias signal, and
a delay circuit which includes a plurality of delay stages for exchanging and outputting a first current variable according to the first bias signal superposed with other signals by the first superposing means and a second current variable according to the second bias signal superposed with other signals by the second superposing means according to levels of input signals, inputs the reference signal to a first delay, and outputs an output signal of one of the delay stages as the feedback signal to the phase comparison means.

4 more elements

Dependencies are inferred from the claim text.

Phase-locked loop circuit and delay-locked loop circuit

Life of this patent

Phase-locked loop circuit and delay-locked loop circuit

Life of this patent

Abstract

Claims46