Phase locked loop circuit having regulator

A circuit, comprising:

• a voltage regulator configured to provide an output voltage;
• a phase frequency detector configured to compare phases and frequencies between a reference clock and a feedback clock, and outputs a clock resulting from the comparison on an output;
• a charge pump configured to output an electric charge on an output in accordance with the output from the phase frequency detector;
• a first path setting section configured to couple the output of the phase frequency detector to the voltage regulator in a first mode of operation such that the output voltage of the voltage regulator is based on the output of the phase frequency detector in the first mode of operation, couple the output of the phase frequency detector to the charge pump in a second mode of operation and switch between the first mode of operation and the second mode of operation;
• a low pass filter configured to store the electric charge output from the charge pump to output a first control voltage on an output;
• a control-voltage generating circuit configured to output a second control voltage on an output, wherein the second control voltage is obtained by dividing the output voltage of the voltage regulator;
• a voltage controlled oscillator configured to output an output clock;
• a second path setting section configured to couple the output of the control-voltage generating circuit to the low pass filter in the first mode of operation, de-couple the output of the control-voltage generating circuit from the low pass filter in the second mode of operation and switch between the first mode of operation and the second mode of operation such that the output of the voltage controlled oscillator is based on the output of the charge pump and the second control voltage in the first mode of operation and on the output of the charge pump in the second mode of operation.

A circuit, comprising:

• a voltage regulator configured to provide an output voltage;
• a phase frequency detector configured to compare phases and frequencies between a reference clock and a feedback clock, and outputs a clock resulting from the comparison on an output;
• a first charge pump configured to output an electric charge in accordance with the output from the phase frequency detector;
• a second charge pump configured to output an electric charge in accordance with the output from the phase frequency detector;
• a first path setting section configured to couple the output of the phase frequency detector to the voltage regulator in a first mode of operation such that the output voltage of the voltage regulator is based on the output of the phase frequency detector in the first mode of operation, couple the output of the phase frequency detector to the first charge pump and the second charge pump in a second mode of operation and switch between the first mode of operation and the second mode of operation;
• a first low pass filter configured to store the electric charge injected from the first charge pump to output a first control voltage on an output;
• a second low pass filter configured to store the electric charge injected from the second charge pump to output a second control voltage on an output;
• a first control-voltage generating circuit configured to output a third control voltage on an output, wherein the third control voltage is obtained by dividing the output voltage of the voltage regulator;
• a second control-voltage generating circuit configured to output a fourth control voltage on an output, wherein the fourth control voltage is obtained by dividing the output voltage of the voltage regulator;
• a differential voltage controlled oscillator which outputs an output clock;
• a second path setting section configured to couple the output of the first control-voltage generating circuit and the output of the second control-voltage generating circuit to the voltage controlled oscillator in the first mode of operation, couple the output of the first low pass filter and the output of the second low pass filter to the voltage controlled oscillator in the second mode of operation and switch between the first mode of operation and the second mode of operation such that the voltage controlled oscillator produces the output clock in accordance with the third control voltage, the fourth control voltage and the output voltage of the voltage regulator in the first mode of operation and produces the output clock in accordance with the first control voltage, the second control voltage and the output voltage of the voltage regulator in the second mode of operation;
• and
• a divider which outputs the feedback clock, wherein the feedback clock is obtained by dividing the output clock of the voltage controlled oscillator to the phase frequency detector.

A method of operating a phase locked loop comprising:

• switching between a first mode of operation and a second mode of operation based on an event, wherein:
• the first mode of operation comprises:
• regulating an output voltage of a voltage regulator based upon the output of a phase frequency detector,
• providing a second control voltage to a voltage controlled oscillator, wherein the first control voltage is obtained by dividing the output voltage of the voltage regulator, and
• producing an output clock from a voltage controlled oscillator in accordance with the first control voltage and the output voltage of the voltage regulator;
• and
• the second mode of operation comprises:
• providing the output of a phase frequency detector to a charge pump configured to produce an electric charge in accordance with the output from the phase frequency detector
• providing a second control voltage to the voltage controlled oscillator from a low pass filter configured to store the electric charge injected from the charge pump and produce the second control voltage;
• providing the output voltage of a voltage regulator to the voltage controlled oscillator;
• and
• producing the output clock from the voltage controlled oscillator in accordance with the second control voltage and the output voltage of the voltage regulator.

A system, comprising:

• a CPU configured to produce a mode signal;
• a power-supply detecting circuit configured to determine a power-supply voltage and produce the mode signal based upon the determined power-supply voltage;
• and
• a phase locked loop (PLL) circuit which outputs a clock signal based upon the mode signal,
• the PLL circuit including:
• a voltage regulator configured to provide an output voltage;
• a phase frequency detector configured to compare phases and frequencies between a reference clock and a feedback clock, and outputs a clock resulting from the comparison on an output;
• a charge pump configured to output an electric charge in accordance with the output from the phase frequency detector;
• a first path setting section configured to couple the output of the phase frequency detector to the voltage regulator in a first mode of operation such that the output voltage of the voltage regulator is based on the output of the phase frequency detector in the first mode of operation, couple the output of the phase frequency detector to the charge pump in a second mode of operation and switch between the first mode of operation and the second mode of operation based upon the mode signal;
• a low pass filter configured to store the electric charge injected from the charge pump to output a first control voltage on an output;
• a control-voltage generating circuit configured to output a second control voltage on an output, wherein the second control voltage is obtained by dividing the output voltage of the voltage regulator;
• a voltage controlled oscillator configured to output an output clock;
• a second path setting section configured to couple the output of the control-voltage generating circuit to the voltage controlled oscillator in a first mode of operation, couple the output of the low pass filter to the voltage controlled oscillator in a second mode of operation and switch between the first mode of operation and the second mode of operation based upon the mode signal such that the voltage controlled oscillator produces the output clock in accordance with the second control voltage and the output voltage of the voltage regulator in the first mode of operation and the voltage controlled oscillator produces the output clock in accordance with the first control voltage and the output voltage of the voltage regulator in the second mode of operation;
• and
• a divider configured to output the feedback clock, wherein the feedback clock is obtained by dividing the output clock of the voltage controlled oscillator to the phase frequency detector.