Dual loop charge pump for enhanced reliability and power consumption
AssigneeInternational Business Machines Corporation
InventorsJames Strom, John Borkenhagen, Ann Chen Wu, Rashmi Bindu
Life of this patent
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Abstract
Embodiments of the present disclosure provide an enhanced phase-locked loop (PLL) circuit and an enhanced charge pump circuit used for various applications, including high-speed data clock generation for complex integrated circuit (IC) designs. The disclosed PLL circuit and charge pump circuit enable significant power and supply current reduction, improved circuit reliability; reduced self-heating and electro-migration risk, and enable use of lower power operational amplifiers with the operational amplifiers driving high impedance nodes.
Claims18
A charge pump circuit comprising:
- an H-bridge circuit;
- an input of the H-bridge circuit coupled to a phase frequency detector to receive respective increment and decrement control signals from the phase frequency detector;
- an output of the H-bridge circuit coupled to a loop filter to control current flow to and from the loop filter based on the respective increment and decrement control signals;
- a first loop control comprising a sense operational amplifier coupled to the H-bridge circuit, wherein the sense operational amplifier provides an output configured to drive a pair of H-bridge footer transistors providing a charge pump current to match respective voltages at a first charge pump node and a second charge pump node;
- and
- a second loop control coupled to the H-bridge circuit configured to drive an H-bridge header transistor to adjust a common mode voltage at the second charge pump node and a third charge pump node, the second charge pump node and the third charge pump node coupled to the loop filter.
A phase-locked loop (PLL) circuit comprising:
- a reference clock signal;
- a voltage controlled oscillator (VCO) circuit having a VCO output frequency controlled by a input control voltage;
- a feedback divider coupled to the VCO circuit dividing the VCO output frequency to provide a feedback clock signal;
- a phase frequency detector coupled to the feedback divider comparing the reference clock signal and the feedback clock signal, the phase frequency detector generating respective increment and decrement control signals based on comparing the reference clock signal and the feedback clock signal;
- a charge pump circuit comprising an input coupled to the phase frequency detector to receive the respective increment and decrement control signals and an output coupled to a loop filter to control current flow to charge, or to discharge at least one capacitor of the loop filter based on the respective increment and decrement control signals;
- the charge pump circuit comprising a first loop control comprising a sense operational amplifier that provides an output configured to drive a pair of charge pump footer transistors providing a charge pump current to match respective voltages at a first charge pump node and a second charge pump node;
- and a second loop control configured to drive a charge pump header transistor to adjust a common mode voltage at the second charge pump node and a third charge pump node, the second charge pump node and the third charge pump node coupled to the loop filter;
- and
- the loop filter providing the input control voltage to the VCO circuit.
Dependencies are inferred from the claim text.